US3835336A
Expired / Lapsed
US
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Pulse width sensing circuit
Assignee: RCA Corp
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Filing: 1973-03-23
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Granted: 1974-09-10
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Expires: 1993-03-23
Abstract
Abstract A circuit for producing an output signal indicative of the presence of an input signal of duration greater than a given duration, T. The circuit includes a first stage which in response to a sampling pulse and the presence of an input signal of first value, stores a signal of first binary significance. The circuit also includes a second stage which in response to a shift pulse occurring a time T after the sampling pulse produces at its output, which is the circuit output, a signal corresponding to the one stored in said first stage. Each stage includes means responsive to the input signal for resetting the output of each stage to a level of second binary significance when the input signal has a second value. A signal of first value must, therefore, be present for a duration greater than T to produce an output of first binary significance, where the duration must also include a sampling pulse followed by a shift pulse. The circuit also includes means for, selectively, directly passing the input signals from the input to the output of the circuit.
Inventors
- 👤 D Block
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 04:51
CPC Classifications
G; G01; G01R; G01R29/00; G01R29/02; G01R29/027; G01R29/0273
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
190 words
The combination comprising: an input terminal for the application thereto of an input signal; first and second means; means for applying sampling pulses to said first means and means for applying shift pulses to said second means, where each shift pulse occurs a time T after a sampling pulse; first and second signal storing means; means coupling said first means between said input terminal and said first storing means, said first means being responsive to the presence of an input signal and a sampling pulse for setting said first storing means to a first condition indicative of the presence of a signal; means coupling said second means between said first and second storing means, said second means being responsive to the presence of a shift pulse and the signal stored in said first storing means for setting said second storing means to the condition stored in said first storing means; and means coupled to said first and second storing means and responsive to the absence of a said input signal for setting said first and second storing means to a second condition indicative of the absence of an input signal.
Claim 2
Dependent Claim
190 words
The combination comprising: an input terminal for the application thereto of an input signal; first and second means; means for applying sampling pulses to said first means and means for applying shift pulses to said second means, where each shift pulse occurs a time T after a sampling pulse; first and second signal storing means; means coupling said first means between said input terminal and said first storing means, said first means being responsive to the presence of an input signal and a sampling pulse for setting said first storing means to a first condition indicative of the presence of a signal; means coupling said second means between said first and second storing means, said second means being responsive to the presence of a shift pulse and the signal stored in said first storing means for setting said second storing means to the condition stored in said first storing means; and means coupled to said first and second storing means and responsive to the absence of a said input signal for setting said first and second storing means to a second condition indicative of the absence of an input signal.
Claim 3
Dependent Claim
147 words
The combination as claimed in claim 1 wherein each one of said signal storing meAns includes, two inverting means each having an input and an output and a transmission gate; one inverting means being connected at its input to the output of the other inverting means and wherein said transmission gate is coupled between the input of the other inverting means and the output of said one inverting means; wherein each one of said first and second means includes a transmission gate means coupled to the input of one of the two inverting means of the storing means to which it is coupled; and wherein said means coupled to said first and second storing means includes an inverter having an input and an output, wherein the inverter input is connected to said input terminal and the inverter output is connected to said first and second storing means.
Claim 4
Dependent Claim
60 words
The combination as claimed in claim 2 wherein said means for applying sampling pulses to said first means includes means for applying said sampling pulses to the transmission gate of said first means, and wherein said means for applying shift pulses to said second means includes means for applying said shift pulses to the transmission gate of said second means.
Claim 5
Dependent Claim
89 words
The combination as claimed in claim 3 wherein said means for applying said sampling and shift pulses include means for applying the complement of said signals; wherein the complement of said sampling pulses are applied to the transmission gate of said first storing means for opening it when the transmission gate of said first means is closed; and wherein the complement of said shift pulses are applied to the transmission gate of said second storing means for opening it when the transmission gate of said second means is closed.
Claim 6
Dependent Claim
84 words
The combination as claimed in claim 1 wherein each one of said storing means has a set input and a reset input and an output; wherein said first means includes a transmission gate, responsive to said sampling pulses, coupled between said input terminal and the set input of said first storing means; and wherein said second means includes a transmission gate responsive to said shift pulses coupled between the output of said first storing means and the set input of said second storing means.
Claim 7
Dependent Claim
44 words
The combination as claimed in claim 5 wherein said means responsive to the absence of a signal include means for inverting the signal present at said input terminal and supplying the inverted signal to the reset input of said first and second storing means.
Claim 8
Dependent Claim
57 words
The combination as claimed in claim 1 further including means responsive to a control signal for setting said second storing means to a condition enabling the passage of an input signal from said input terminal to the output of said second signal storing means without the signal being delayed by said sampling pulse or said shift pulse.
Claim 9
Dependent Claim
173 words
The combination comprising: an input terminal for the application thereto of input signals; first and second two state storing means, each having a set input, a reset input and an output; first transmission gate means coupled between said input terminal and the set input of said first storing means; second transmission gate means coupled between the output of said first storing means and the set input of said second storing means; means for enabling said first transmission gate means for setting said first storing means to one binary condition during a sampling interval in response to an input signal of one value; means for enabling said second transmission gate means for setting said second storing means to said one binary condition during a shift interval, said shift interval occurring a time T after said sampling interval; and means coupled to the reset inputs of said first and second storing means responsive to said input signals having a second value for setting said first storing and second storing means to the other binary condition.
Claim 10
Dependent Claim
173 words
The combination comprising: an input terminal for the application thereto of input signals; first and second two state storing means, each having a set input, a reset input and an output; first transmission gate means coupled between said input terminal and the set input of said first storing means; second transmission gate means coupled between the output of said first storing means and the set input of said second storing means; means for enabling said first transmission gate means for setting said first storing means to one binary condition during a sampling interval in response to an input signal of one value; means for enabling said second transmission gate means for setting said second storing means to said one binary condition during a shift interval, said shift interval occurring a time T after said sampling interval; and means coupled to the reset inputs of said first and second storing means responsive to said input signals having a second value for setting said first storing and second storing means to the other binary condition.
Claim 11
Dependent Claim
166 words
The combination as claimed in claim 8 wherein said second storing means includes first and second two input NOR Gates, and a transmission gate; the output of the first NOR gate being connected to one input of the second NOR gate and the transmission gate coupling the output of the second NOR gate to one input of the first NOR gate; means for directly applying the complement of the input signal to the other input of said NOR gate; means for applying a control signal to the other input of said first NOR gate for producing at its output a signal enabling the signal present at the other input of said second NOR gate to pass through said second NOR gate without delay; and wherein said means coupled to the reset inputs includes an inverter having an input and an output, wherein the input of the inverter is connected to said input terminal and wherein the output of the inverter is connected to said reset inputs.
Claim 12
Dependent Claim
65 words
The combination as claimed in claim 9 wherein said transmission gate means includes two complementary insulated-gate field-effect transistors having their conduction paths connected in parallel; wherein each one of said first and second storing means includes an inverter and a two input NOR gate cross coupled to form a flip-flop; and wherein said inverter and said NOR gate are comprised of complementary insulated-gate field-effect transistors.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1977-09-09 | 1978-03-11 | 1978-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1981-09-09 | 1982-03-11 | 1982-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1985-09-09 | 1986-03-11 | 1986-09-10 | $7700.00 | Window Closed / Lapsed |