Method to prevent passivation from keyhole damage and resist extrusion

Claim 1

A method of fabricating an integrated circuit device comprising: providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures are covered by an insulating layer; depositing and patterning a metal layer overlying said insulating layer to form metal lines wherein there is a gap between two of said metal lines; depositing a passivation layer overlying said metal lines wherein said gap is not filled completely by said passivation layer; coating said passivation layer with a hydrophillic solvent comprising glycerol wherein said hydrophillic solvent completely fills said gap; coating said passivation layer with a photoresist layer and exposing and developing-said photoresist layer to form a photoresist mask; etching away said passivation layer where it is not covered by said photoresist mask over one of said metal lines which forms a bonding pad; and removing said photoresist mask to complete the fabrication of said integrated circuit device.

Claim 2

A method of fabricating an integrated circuit device comprising: providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures are covered by an insulating layer; depositing and patterning a metal layer overlying said insulating layer to form metal lines wherein there is a gap between two of said metal lines; depositing a passivation layer overlying said metal lines wherein said gap is not filled completely by said passivation layer; coating said passivation layer with a hydrophillic solvent comprising glycerol wherein said hydrophillic solvent completely fills said gap; coating said passivation layer with a photoresist layer and exposing and developing-said photoresist layer to form a photoresist mask; etching away said passivation layer where it is not covered by said photoresist mask over one of said metal lines which forms a bonding pad; and removing said photoresist mask to complete the fabrication of said integrated circuit device.

Claim 10

A method of fabricating an integrated circuit device comprising: providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures are covered by an insulating layer; depositing and patterning a metal layer overlying said insulating layer to form metal lines wherein there is a gap between two of said metal lines; depositing a passivation layer overlying said metal lines wherein a keyhole is formed within said passivation layer within said gap; coating said passivation layer with a hydrophillic solvent wherein said hydrophillic solvent flows into said keyhole; coating said passivation layer with a photoresist layer wherein said hydrophillic solvent within said keyhole prevents said photoresist from sinking into said keyhole resulting in a uniform thickness photoresist layer; exposing and developing said photoresist layer to form a photoresist mask; etching away said passivation layer where it is not covered by said photoresist mask over one of said metal lines which forms a bonding pad; and removing said photoresist mask to complete the fabrication of said integrated circuit device.

Claim 11

A method of fabricating an integrated circuit device comprising: providing semiconductor device structures in and on a semiconductor substrate wherein said semiconductor device structures are covered by an insulating layer; depositing and patterning a metal layer overlying said insulating layer to form metal lines wherein there is a gap between two of said metal lines; depositing a passivation layer overlying said metal lines wherein a keyhole is formed within said passivation layer within said gap; coating said passivation layer with a hydrophillic solvent wherein said hydrophillic solvent flows into said keyhole; coating said passivation layer with a photoresist layer wherein said hydrophillic solvent within said keyhole prevents said photoresist from sinking into said keyhole resulting in a uniform thickness photoresist layer; exposing and developing said photoresist layer to form a photoresist mask; etching away said passivation layer where it is not covered by said photoresist mask over one of said metal lines which forms a bonding pad; and removing said photoresist mask to complete the fabrication of said integrated circuit device.

Claim 18

A method of fabricating an integrated circuit device comprising: providing gate electrodes in and on a semiconductor substrate and forming associated source and drain regions within said semiconductor substrate; covering said gate electrodes with a first dielectric layer; forming electrical connections to said source and drain regions and to said gate electrode by depositing a first metal layer through openings in said first dielectric layer; forming succeeding levels of intervening dielectric layers and metal layers overlying said first metal layer with appropriate electrical connections wherein said topmost level comprises a dielectric layer; depositing and patterning a topmost metal layer overlying said topmost dielectric layer to form metal lines wherein there is a gap between two of said metal lines; depositing a passivation layer overlying said metal lines wherein a keyhole is formed within said passivation layer within said gap; coating said passivation layer with a hydrophillic solvent comprising glycerol wherein said hydrophillic solvent flows into said keyhole; coating said passivation layer with a photoresist layer wherein said hydrophillic solvent within said keyhole prevents said photoresist from sinking into said keyhole resulting in a uniform thickness photoresist layer; exposing and developing said photoresist layer to form a photoresist mask; etching away said passivation layer where it is not covered by said photoresist mask over one of said metal lines which forms a bonding pad; and removing said photoresist mask to complete the fabrication of said integrated circuit device.

Claim 19

A method of fabricating an integrated circuit device comprising: providing gate electrodes in and on a semiconductor substrate and forming associated source and drain regions within said semiconductor substrate; covering said gate electrodes with a first dielectric layer; forming electrical connections to said source and drain regions and to said gate electrode by depositing a first metal layer through openings in said first dielectric layer; forming succeeding levels of intervening dielectric layers and metal layers overlying said first metal layer with appropriate electrical connections wherein said topmost level comprises a dielectric layer; depositing and patterning a topmost metal layer overlying said topmost dielectric layer to form metal lines wherein there is a gap between two of said metal lines; depositing a passivation layer overlying said metal lines wherein a keyhole is formed within said passivation layer within said gap; coating said passivation layer with a hydrophillic solvent comprising glycerol wherein said hydrophillic solvent flows into said keyhole; coating said passivation layer with a photoresist layer wherein said hydrophillic solvent within said keyhole prevents said photoresist from sinking into said keyhole resulting in a uniform thickness photoresist layer; exposing and developing said photoresist layer to form a photoresist mask; etching away said passivation layer where it is not covered by said photoresist mask over one of said metal lines which forms a bonding pad; and removing said photoresist mask to complete the fabrication of said integrated circuit device.