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US5985747A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device manufacturing method

Assignee: Sony Corp
•
Filing: 1997-10-09
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Granted: 1999-11-16
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Expires: 2017-10-09
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Abstract

Abstract An underlying Al alloy wiring 3 and an inter-layer insulation film 4 are formed sequentially on a semiconductor substrate 1 via an inter-layer insulation film 2. An inter-layer insulation film 5 highly hygroscopic and containing much moisture is made and etched back to flush depressions by the underlying Al alloy wiring 3. After an inter-layer insulation film 6 is made, a contact-hole C is made in the inter-layer insulation films 6 and 4. After that, prior to making a TiN/Ti film 7, gases are removed from the inter-layer insulation films 4 through 6 by annealing. The TiN/Ti film 7 is made as thick as 80 nm. In an alternative version, after the inter-layer insulation film is etched back, annealing is done to remove gases especially from the inter-layer insulation film 5. In another alternative version, a protective film 9 is made on the side wall of the contact-hole C, or the surface of the inter-layer insulation films 6 and 4 having formed the contact-hole or the surface of the inter-layer insulation film 5, is nitrified, to prevent degassing of the inter-layer insulation films 4 through 6.

Inventors

  • 👤 Mitsuru Taguchi

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 17:26
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10W20/059; H10W20/032; H10W20/033; H10P; H10P14/00; H10P14/60; H10P14/69; H10P14/694; H10P14/6943; H10P14/69433; H10W20/071; H10W20/074; H10W20/076; H10W20/081; H10W20/093; H10W20/096; H10W20/097; H10W20/40; H10W20/41; H10W20/42; H10W20/425

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 85 words
A semiconductor device manufacturing method comprising the steps of: making an inter-layer insulation film at least partly made of an inter-layer insulation film material containing moisture; making an opening in said inter-layer insulation film; annealing said inter-layer insulation film to release a gas of water from said inter-layer insulation film material; making a film of a wiring material on said inter-layer insulation film having formed said opening; and plugging said wiring material into said opening of the inter-layer insulation film by a high-pressure reflow process.
Claim 2
Dependent Claim 85 words
A semiconductor device manufacturing method comprising the steps of: making an inter-layer insulation film at least partly made of an inter-layer insulation film material containing moisture; making an opening in said inter-layer insulation film; annealing said inter-layer insulation film to release a gas of water from said inter-layer insulation film material; making a film of a wiring material on said inter-layer insulation film having formed said opening; and plugging said wiring material into said opening of the inter-layer insulation film by a high-pressure reflow process.
Claim 3
Dependent Claim 58 words
The semiconductor device manufacturing method according to claim 1 wherein the step of annealing the inter-layer insulation film, the step of making a film of the wiring material and the step of plugging the wiring material into the opening by the high-pressure reflow process are executed continuously in a vacuum without exposing the product into the atmospheric air.
Claim 4
Dependent Claim 36 words
The semiconductor device manufacturing method according to claim 1 wherein the step of annealing the inter-layer insulation film is done before another inter-layer insulation film material makes a film on the moisture-containing inter-layer insulation film material.
Claim 5
Dependent Claim 45 words
The semiconductor device manufacturing method according to claim 1 wherein the step of annealing the inter-layer insulation film is subsequent to the step of making the opening in the inter-layer insulation film and prior to the step of making the film of the wiring material.
Claim 6
Dependent Claim 32 words
The semiconductor device manufacturing method according to claim 1 wherein the step of annealing the inter-layer insulation film is done at a temperature in the range from 430° C. to 550° C.
Claim 7
Dependent Claim 32 words
The semiconductor device manufacturing method according to claim 1 wherein the step of annealing the inter-layer insulation film is done at a temperature in the range from 450° C. to 500° C.
Claim 8
Dependent Claim 15 words
The semiconductor device manufacturing method according to claim 1 wherein said opening is a contact-hole.
Claim 9
Dependent Claim 19 words
The semiconductor device manufacturing method according to claim 1 wherein said opening is a groove for a damascene wiring.
Claim 10
Dependent Claim 60 words
The semiconductor device manufacturing method according to claim 1 wherein the amount of water molecules released from the inter-layer insulation film during the process from the step of making the film of the wiring material to the step of plugging the wiring material in the opening by the high-pressure reflow process is not larger than 5×10 17 /cm 2 .

References Cited (Backward Citations)

US5650360A Cited
US5716869A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-11-15 2003-05-17 2003-11-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-11-15 2007-05-17 2007-11-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-11-15 2011-05-17 2011-11-16 $7700.00 Window Closed / Lapsed

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