Method for manufacturing semiconductor device with multilayer wiring structure, including improved step of forming insulating film which covers wiring layer

Claim 1

A method for manufacturing a semiconductor device having a multilayer wiring structure, in which the step of forming a insulating film for covering a wiring layer is improved, comprising the steps of: forming a wiring pattern on an insulating film provided on a semiconductor substrate; forming a reflow film by introducing SiH 4 gas and H 2 O 2 into a reaction chamber in which the semiconductor substrate provided with the wiring pattern is placed, and by reacting them with each other under a negative pressure of 665 Pa or less and at a temperature falling within a range from -10° C. to +10° C., thereby forming a reflow SiO 2 film of a reflow configuration on the wiring pattern leaving side portions of the wiring pattern partially exposed; and forming a plasma CVD insulating film by depositing continuously the plasma CVD insulating film on the reflow SiO 2 film on the semiconductor substrate by plasma CVD under a negative such that the plasma CVD insulating film covers the partially exposed side portions of the wiring pattern pressure.

Claim 2

A method for manufacturing a semiconductor device having a multilayer wiring structure, in which the step of forming a insulating film for covering a wiring layer is improved, comprising the steps of: forming a wiring pattern on an insulating film provided on a semiconductor substrate; forming a reflow film by introducing SiH 4 gas and H 2 O 2 into a reaction chamber in which the semiconductor substrate provided with the wiring pattern is placed, and by reacting them with each other under a negative pressure of 665 Pa or less and at a temperature falling within a range from -10° C. to +10° C., thereby forming a reflow SiO 2 film of a reflow configuration on the wiring pattern leaving side portions of the wiring pattern partially exposed; and forming a plasma CVD insulating film by depositing continuously the plasma CVD insulating film on the reflow SiO 2 film on the semiconductor substrate by plasma CVD under a negative such that the plasma CVD insulating film covers the partially exposed side portions of the wiring pattern pressure.

Claim 6

A method for manufacturing a semiconductor device having a multilayer wiring structure, in which the step of forming a insulating film for covering a wiring layer is improved, comprising the steps of: forming a wiring pattern on an insulating film provided on a semiconductor substrate; forming a reflow film by introducing SiH 4 gas and H 2 O 2 into a reaction chamber in which the semiconductor substrate provided with the wiring pattern is placed, and by reacting them with each other under a negative pressure of 665 Pa or less and at a temperature falling within a range from -10° C. to +10° C., thereby forming a reflow SiO 2 film of a reflow configuration on the wiring pattern leaving side portions of the wiring pattern partially exposed; forming a plasma CVD insulating film by depositing continuously the plasma CVD insulating film on the reflow SiO 2 film on the semiconductor substrate by plasma CVD under a negative such that the plasma CVD insulating film covers the partially exposed side portions of the wiring pattern pressure; and heating the resultant semiconductor substrate for 30 minutes or more at a high temperature falling within a range from 400° C. to 450° C.

Claim 7

A method for manufacturing a semiconductor device having a multilayer wiring structure, in which the step of forming a insulating film for covering a wiring layer is improved, comprising the steps of: forming a wiring pattern on an insulating film provided on a semiconductor substrate; forming a reflow film by introducing SiH 4 gas and H 2 O 2 into a reaction chamber in which the semiconductor substrate provided with the wiring pattern is placed, and by reacting them with each other under a negative pressure of 665 Pa or less and at a temperature falling within a range from -10° C. to +10° C., thereby forming a reflow SiO 2 film of a reflow configuration on the wiring pattern leaving side portions of the wiring pattern partially exposed; forming a plasma CVD insulating film by depositing continuously the plasma CVD insulating film on the reflow SiO 2 film on the semiconductor substrate by plasma CVD under a negative such that the plasma CVD insulating film covers the partially exposed side portions of the wiring pattern pressure; and heating the resultant semiconductor substrate for 30 minutes or more at a high temperature falling within a range from 400° C. to 450° C.