Patent US6140238A successfully refreshed from Google Patents.
US6140238A
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Self-aligned copper interconnect structure and method of manufacturing same
Assignee: National Semiconductor Corp
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Filing: 1999-04-21
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Granted: 2000-10-31
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Expires: 2019-04-21
Abstract
Abstract A copper interconnect structure is formed in a semiconductor device using self-aligned copper or tungsten via pillars to connect upper and lower copper interconnect layers separated by a dielectric. The lower copper interconnect layer is formed on an underlying layer. The via pillars are formed on the lower copper interconnect layer. The copper upper interconnect layer is formed to make electrical contact to exposed upper surfaces of the via pillars.
Inventors
- 👤 Vassili Kitch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:29
CPC Classifications
H; H10; H10W; H10W10/00; H10W20/00; H10W20/01; H10W20/031; H10W20/069; H10W10/01; H10W20/063; H10W20/0633; H10W20/0693; H10W20/056
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
294 words
A method of forming a conductive via between a lower copper interconnect layer and an upper copper interconnect layer in a semiconductor device structure, the method comprising: forming a lower conductive diffusion barrier layer on an underlying layer as part of the semiconductor device structure; forming a first copper layer on the lower diffusion barrier layer; forming an etch stop layer on the first copper layer, the etch stop layer having a high etch selectivity with respect to copper; forming a second copper layer on the etch stop layer; forming a layer hardmask material on the second copper layer; patterning the layer of hardmask material to define a patterned hardmask; using the patterned hardmask to etch the second copper layer, the etch stop layer, the first copper layer and the lower diffusion barrier layer to form a patterned metal stack and to expose portions of the underlying layer; forming a layer of dielectric diffusion barrier material over the patterned metal stack; forming a first dielectric layer such that the first dielectric layer fills gaps between the patterned metal stack; planarizing the first dielectric layer to expose an upper surface of the second copper layer; etching regions of the second copper layer using the etch stop layer as an etch stop, thereby defining spaced-apart copper via pillars; forming a second dielectric diffusion barrier layer over the copper via pillars; forming a second dielectric layer such that the second dielectric layer fills gaps between the copper via pillars; planarizing the second dielectric layer to expose an upper surface of the copper via pillars; and forming a patterned upper copper interconnect layer overlying the exposed copper via pillars, whereby the copper via pillars form vias between the lower copper interconnect layer and the upper copper interconnect layer.
Claim 2
Independent Claim
294 words
A method of forming a conductive via between a lower copper interconnect layer and an upper copper interconnect layer in a semiconductor device structure, the method comprising: forming a lower conductive diffusion barrier layer on an underlying layer as part of the semiconductor device structure; forming a first copper layer on the lower diffusion barrier layer; forming an etch stop layer on the first copper layer, the etch stop layer having a high etch selectivity with respect to copper; forming a second copper layer on the etch stop layer; forming a layer hardmask material on the second copper layer; patterning the layer of hardmask material to define a patterned hardmask; using the patterned hardmask to etch the second copper layer, the etch stop layer, the first copper layer and the lower diffusion barrier layer to form a patterned metal stack and to expose portions of the underlying layer; forming a layer of dielectric diffusion barrier material over the patterned metal stack; forming a first dielectric layer such that the first dielectric layer fills gaps between the patterned metal stack; planarizing the first dielectric layer to expose an upper surface of the second copper layer; etching regions of the second copper layer using the etch stop layer as an etch stop, thereby defining spaced-apart copper via pillars; forming a second dielectric diffusion barrier layer over the copper via pillars; forming a second dielectric layer such that the second dielectric layer fills gaps between the copper via pillars; planarizing the second dielectric layer to expose an upper surface of the copper via pillars; and forming a patterned upper copper interconnect layer overlying the exposed copper via pillars, whereby the copper via pillars form vias between the lower copper interconnect layer and the upper copper interconnect layer.
Claim 3
Dependent Claim
17 words
A method as in claim 1, and wherein the underlying layer comprises a layer of dielectric material.
Claim 4
Dependent Claim
35 words
A method as in claim 1, and wherein the diffusion barrier layer is formed of a material selected from the group consisting of tantalum, tantalum nitride, tungsten, tungsten nitride, titanium, titanium nitride, and combinations thereof.
Claim 5
Dependent Claim
16 words
A method as in claim 1, and wherein the dielectric diffusion barrier layer comprises silicon oxynitride.
Claim 6
Dependent Claim
16 words
A method as in claim 1, and wherein the dielectric diffusion barrier layer comprises silicon nitride.
Claim 7
Dependent Claim
31 words
A method as in claim 1, and wherein the etch stop layer is formed of a material selected from the group consisting of tungsten, tungsten nitride, tungsten silicide, and combinations thereof.
Claim 8
Dependent Claim
16 words
A method as in claim 1, and wherein the hardmask material comprises an oxide of silicon.
Claim 9
Dependent Claim
14 words
A method as in claim 1, and wherein the hardmask material is silicon dioxide.
Claim 10
Dependent Claim
71 words
An interconnect structure formed as part of a semiconductor device structure, the interconnect structure comprising: a conductive patterned lower interconnect layer formed on an underlying layer as part of the semiconductor device structure; conductive via pillars formed in spaced-apart relationship on an upper surface of the lower interconnect layer, the via pillars including copper or tungsten; and a conductive patterned upper interconnect layer formed in electrical contact with the via pillars.
Claim 11
Dependent Claim
71 words
An interconnect structure formed as part of a semiconductor device structure, the interconnect structure comprising: a conductive patterned lower interconnect layer formed on an underlying layer as part of the semiconductor device structure; conductive via pillars formed in spaced-apart relationship on an upper surface of the lower interconnect layer, the via pillars including copper or tungsten; and a conductive patterned upper interconnect layer formed in electrical contact with the via pillars.
Claim 12
Dependent Claim
44 words
A interconnect structure as in claim 9, and wherein the lower interconnect layer includes a diffusion barrier layer formed on the underlying layer, a first copper layer formed on the diffusion barrier layer and an etch stop layer formed on the first copper layer.
Claim 13
Dependent Claim
25 words
An interconnect structure as in claim 10, and wherein sidewalls of the lower interconnect layer are covered by a layer of dielectric diffusion barrier material.
Claim 14
Dependent Claim
20 words
An interconnect structure as in claim 11, and wherein the dielectric diffusion barrier material comprises silicon oxynitride or silicon nitride.
Claim 15
Dependent Claim
21 words
An interconnect structure as in claim 11, and wherein sidewalls of the via pillars are covered by dielectric diffusion barrier material.
Claim 16
Dependent Claim
34 words
An interconnect structure as in claim 10, and wherein the diffusion barrier layer comprises a material selected from the group consisting of tantalum, tantalum nitride, tungsten, tungsten nitride, titanium, titanium nitride, and combinations thereof.
Claim 17
Dependent Claim
34 words
An interconnect structure as in claim 10, and wherein the etch stop layer comprises a material selected from the group consisting of tungsten, tungsten nitride, tungsten silicide, titanium nitride, tanatalum nitride, and combinations thereof.
Claim 18
Dependent Claim
26 words
An interconnect structure as in claim 9, and wherein the via pillars comprise a second copper or a tungsten layer formed on the lower interconnect layer.
Claim 19
Dependent Claim
15 words
An interconnect structure as in claim 9, and wherein the upper interconnect layer includes copper.
Claim 20
Independent Claim
288 words
A method of forming a conductive via between a lower copper interconnect layer and an upper copper interconnect layer in a semiconductor device structure, the method comprising: forming a lower conductive diffusion barrier layer on an underlying layer as part of the semiconductor device structure; forming a first copper layer on the lower diffusion barrier layer; forming an etch stop layer on the first copper layer, the etch stop layer having a high etch selectivity with respect to copper; forming a layer of tungsten on the etch stop layer; forming a patterned photoresist mask on the tungsten layer; using the patterned photoresist mask to etch the tungsten layer to define a patterned tungsten layer; using the patterned tungsten layer as a hardmask to etch the stop layer, the first copper layer and the diffusion barrier layer to define a patterned metal stack; removing the remaining patterned photoresist mask; forming a layer of dielectric diffusion barrier material over the patterned metal stack; forming a first dielectric layer such that the first dielectric layer fills gaps between the patterned metal stack; planarizing the first dielectric layer to expose an upper surface of the tungsten layer; etching regions of the tungsten layer using the etching stop layer as an etch stop, thereby defining space-apart tungsten via pillars; forming a second dielectric diffusion barrier layer over the tungsten via pillars; forming a second dielectric layer such that the second dielectric layer fills gaps between the tungsten via pillars; planarizing the second dielectric layer to expose an upper surface of the tungsten via pillars; and forming a patterned upper copper interconnect layer overlying the exposed tungsten via pillars, whereby the tungsten via pillars form vias between the lower and upper copper interconnect layers.
Claim 21
Independent Claim
288 words
A method of forming a conductive via between a lower copper interconnect layer and an upper copper interconnect layer in a semiconductor device structure, the method comprising: forming a lower conductive diffusion barrier layer on an underlying layer as part of the semiconductor device structure; forming a first copper layer on the lower diffusion barrier layer; forming an etch stop layer on the first copper layer, the etch stop layer having a high etch selectivity with respect to copper; forming a layer of tungsten on the etch stop layer; forming a patterned photoresist mask on the tungsten layer; using the patterned photoresist mask to etch the tungsten layer to define a patterned tungsten layer; using the patterned tungsten layer as a hardmask to etch the stop layer, the first copper layer and the diffusion barrier layer to define a patterned metal stack; removing the remaining patterned photoresist mask; forming a layer of dielectric diffusion barrier material over the patterned metal stack; forming a first dielectric layer such that the first dielectric layer fills gaps between the patterned metal stack; planarizing the first dielectric layer to expose an upper surface of the tungsten layer; etching regions of the tungsten layer using the etching stop layer as an etch stop, thereby defining space-apart tungsten via pillars; forming a second dielectric diffusion barrier layer over the tungsten via pillars; forming a second dielectric layer such that the second dielectric layer fills gaps between the tungsten via pillars; planarizing the second dielectric layer to expose an upper surface of the tungsten via pillars; and forming a patterned upper copper interconnect layer overlying the exposed tungsten via pillars, whereby the tungsten via pillars form vias between the lower and upper copper interconnect layers.
References Cited (Backward Citations)
US4810332A
Cited
US4917759A
Cited
US5258096A
Cited
US5354712A
Cited
US5451543A
Cited
US6037223A
Cited
US6030896A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-31 | 2004-05-01 | 2004-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-31 | 2008-05-01 | 2008-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-31 | 2012-05-01 | 2012-10-31 | $7700.00 | Window Closed / Lapsed |