Method and apparatus for initializing a microprocessor to insure fault-free operation

Claim 2

A data processing system, comprising: a central processing unit (CPU), said CPU having a first possible operating state of fault-free operation and a second possible operating state of fault operation; first means for applying a first signal to said CPU to provide notice of initialization, said CPU operative to complete certain processing tasks in response to said first signal; and second means for applying a second signal to said CPU subsequent to said first signal and upon expiration of a predetermined time interval to cause the initialization of said CPU regardless of whether the CPU is operating in said first possible operating state or said second possible operating state.

Claim 3

The apparatus of claim 1, wherein said CPU comprises means for generating fixed pattern data.

Claim 4

The apparatus of claim 2, wherein said CPU, responsive to said first signal, completes certain processing of operating data and causes the storage of a selected set of said operating data and said fixed pattern data within a memory storage device to provide stored selected data and stored fixed pattern data.

Claim 5

The apparatus of claim 3, wherein said CPU calculates a checksum, representative of the sum of said stored selected data and said stored fixed pattern data, in response to said first signal.

Claim 6

The apparatus of claim 4, wherein said CPU causes the storage of said checksum within said memory storage device to provide a stored checksum in response to said first signal.

Claim 7

The apparatus of claim 5, wherein said CPU, in response to said second signal, verifies the validity of said stored fixed pattern data by comparing said stored fixed pattern data to said fixed pattern data.

Claim 8

The apparatus of claim 6, wherein said CPU clears said stored selected data, said stored fixed pattern data, and said stored checksum from said memory storage device in response to detecting corruption of said stored fixed pattern data.

Claim 9

The apparatus of claim 7, wherein said CPU executes an initial instruction set and builds new operating data in response to clearing said stored selected data, said stored fixed pattern data, and said stored checksum.

Claim 10

The apparatus of claim 6, wherein said CPU verifies the validity of said stored checksum, in response to verifying that said stored fixed pattern data is valid, by calculating the sum of said stored selected data and said stored fixed pattern data to produce a new checksum and comparing said new checksum to said stored checksum.

Claim 11

The apparatus of claim 9, wherein said CPU clears said stored selected data, said stored fixed pattern data, and said stored checksum from said memory storage device in response to detecting corruption of said stored checksum.

Claim 12

The apparatus of claim 10, wherein said CPU executes an initial instruction set and builds new operating data in response to clearing said stored selected data, said stored fixed pattern data, and said stored checksum.

Claim 13

The apparatus of claim 9, wherein said CPU clears said stored fixed pattern data from said memory storage device in response to verifying that said stored checksum is valid.

Claim 14

The apparatus of claim 12, wherein said CPU clears all of said operating data, other than said stored selected data, from said memory storage device in response to clearing said stored fixed pattern data.

Claim 15

The apparatus of claim 13, wherein said CPU executes an initial instruction set using said selected stored data in response to clearing all of said operating data other than said stored selected data.

Claim 16

The apparatus of claim 1, wherein said second signal synchronously resets said first means and said second means.

Claim 17

A data processing system, comprising: first timing means for producing a first timing signal upon expiration of a first time interval to provide notice of an impending initialization; second timing means, synchronized with said first timing means, for producing a second timing signal upon expiration of a second time interval, said second time interval being a greater time interval than said first time interval; a central processing unit (CPU), said CPU having a first possible operating state of fault-free operation and a second possible operating state of fault operation, said CPU being responsive to said first timing signal to complete certain processing tasks and to generate an initialization status signal supplying an indication that said CPU has completed said certain processing tasks and is ready for said impending initialization, wherein said CPU will generate said initialization status signal prior to expiration of said second time interval when said CPU is operating in said first possible operating state; and initialization means, responsive to said initialization status signal, for applying prior to expiration of said second time interval a reset signal to initialize said CPU and a timing reset signal to synchronously reset said first timing means and said second timing means, said CPU being initialized by said reset signal when said CPU is operating in said first possible operating state; said initialization means, responsive to said second timing signal, for applying said reset signal to initialize said CPU and for applying said timing reset signal to synchronously reset said first timing means and said second timing means, said CPU being initialized by said reset signal when said CPU is operating in said second possible operating state.

Claim 18

A data processing system, comprising: first timing means for producing a first timing signal upon expiration of a first time interval to provide notice of an impending initialization; second timing means, synchronized with said first timing means, for producing a second timing signal upon expiration of a second time interval, said second time interval being a greater time interval than said first time interval; a central processing unit (CPU), said CPU having a first possible operating state of fault-free operation and a second possible operating state of fault operation, said CPU being responsive to said first timing signal to complete certain processing tasks and to generate an initialization status signal supplying an indication that said CPU has completed said certain processing tasks and is ready for said impending initialization, wherein said CPU will generate said initialization status signal prior to expiration of said second time interval when said CPU is operating in said first possible operating state; and initialization means, responsive to said initialization status signal, for applying prior to expiration of said second time interval a reset signal to initialize said CPU and a timing reset signal to synchronously reset said first timing means and said second timing means, said CPU being initialized by said reset signal when said CPU is operating in said first possible operating state; said initialization means, responsive to said second timing signal, for applying said reset signal to initialize said CPU and for applying said timing reset signal to synchronously reset said first timing means and said second timing means, said CPU being initialized by said reset signal when said CPU is operating in said second possible operating state.

Claim 19

The apparatus of claim 16, wherein said CPU comprises means for generating fixed pattern data.

Claim 20

The apparatus of claim 17, wherein said CPU, responsive to said first signal and within said second time interval, completes certain processing of operating data and causes the storage of a selected set of said operating data and said fixed pattern data within a memory storage device to provide stored selected data and stored fixed pattern data.

Claim 21

The apparatus of claim 18, wherein said CPU calculates a checksum, representative of the sum of said stored selected data and said stored fixed pattern data, in response to said first timing signal and within said second time interval.

Claim 22

The apparatus of claim 19, wherein said CPU causes the storage of said checksum within said memory storage device to provide a stored checksum in response to said first timing signal and within said second time interval.

Claim 23

The apparatus of claim 20, wherein said CPU generates said initialization status signal in response to the storage of said selected data, said fixed pattern data, and said checksum.

Claim 24

The apparatus of claim 21, wherein said CPU, in response to said reset signal, verifies the validity of said stored fixed pattern data by comparing said stored fixed pattern data to said fixed pattern data.

Claim 25

The apparatus of claim 22, wherein said CPU clears said stored selected data, said stored fixed pattern data, and said stored checksum from said memory storage device in response to detecting corruption of said stored fixed pattern data.

Claim 26

The apparatus of claim 23, wherein said CPU executes an initial instruction set and builds new operating data in response to clearing said stored selected data, said stored fixed pattern data, and said stored checksum.

Claim 27

The apparatus of claim 22, wherein said CPU verifies the validity of said stored checksum in response to verifying that said fixed pattern data is valid, by calculating the sum of said stored selected data and said stored fixed pattern data to produce a new checksum and comparing said new checksum to said stored checksum.

Claim 28

The apparatus of claim 25, wherein said CPU clears said stored selected data, said stored fixed pattern data, and said stored checksum from said memory storage device in response to detecting corruption of said stored checksum.

Claim 29

The apparatus of claim 26, wherein said CPU executes an initial instruction set and builds new operating data in response to clearing said stored selected data, said stored fixed pattern data, and said stored checksum.

Claim 30

The apparatus of claim 25, wherein said CPU clears said stored fixed pattern data from said memory storage device in response to verifying that said stored checksum is valid.

Claim 31

The apparatus of claim 28, wherein said CPU clears all of said operating data, other than said stored selected data, from said memory storage device in response to clearing said fixed pattern data.

Claim 32

The apparatus of claim 29, wherein said CPU executes an initial instruction set using said selected stored data in response to clearing all of said operating data other than said stored selected data.

Claim 33

A data processing system, comprising: first timing means for producing a first timing signal upon expiration of a first time interval to provide notice of an impending initialization; second timing means for producing a second timing signal upon expiration of a second time interval, said second time interval being a greater time interval than said first time interval; computing means for processing operating data, said computing means having a first possible operating state of fault-free operation and a second possible operating state of fault operation, said computing means being responsive to said first timing signal to complete certain processing tasks and to generate an initialization status signal supplying an indication that said computing means has completed said certain processing tasks and is ready for said impending initialization, wherein said computing means will generate said initialization status signal prior to expiration of said second time interval when said computing means is operating in said first possible operating state; memory storage device for storing said operating data; and initialization means, responsive to said initialization status signal, for applying prior to expiration of said second time interval a reset signal for initializing said computing means and a timing reset signal to synchronously reset said first timing means and said second timing means, said computing means being initialized by said reset signal when said computing means is operating in said first possible operating state, said initialization means, responsive to said second timing signal, for applying said reset signal to initialize said computing means and for applying said timing reset signal to synchronously reset said first timing means and said second timing means, said computing means being initialized by said reset signal when said computing means is operating in said second possible operating state.

Claim 34

A data processing system, comprising: first timing means for producing a first timing signal upon expiration of a first time interval to provide notice of an impending initialization; second timing means for producing a second timing signal upon expiration of a second time interval, said second time interval being a greater time interval than said first time interval; computing means for processing operating data, said computing means having a first possible operating state of fault-free operation and a second possible operating state of fault operation, said computing means being responsive to said first timing signal to complete certain processing tasks and to generate an initialization status signal supplying an indication that said computing means has completed said certain processing tasks and is ready for said impending initialization, wherein said computing means will generate said initialization status signal prior to expiration of said second time interval when said computing means is operating in said first possible operating state; memory storage device for storing said operating data; and initialization means, responsive to said initialization status signal, for applying prior to expiration of said second time interval a reset signal for initializing said computing means and a timing reset signal to synchronously reset said first timing means and said second timing means, said computing means being initialized by said reset signal when said computing means is operating in said first possible operating state, said initialization means, responsive to said second timing signal, for applying said reset signal to initialize said computing means and for applying said timing reset signal to synchronously reset said first timing means and said second timing means, said computing means being initialized by said reset signal when said computing means is operating in said second possible operating state.

Claim 35

The apparatus of claim 31, wherein said computing means comprises means for generating fixed pattern data.

Claim 36

The apparatus of claim 32, wherein said computing means operates to complete current processing of said operating data and causes the storage of a selected set of said operating data and said fixed pattern data within said memory storage device to provide stored selected data and stored fixed pattern data in response to said first timing signal and within said second time interval.

Claim 37

The apparatus of claim 33, wherein said computing means calculates a checksum, representative of the sum of said stored selected data and said stored fixed pattern data, and causes the storage of said checksum within said memory storage device to provide a stored checksum in response to said first timing signal and within said second time interval.

Claim 38

The apparatus of claim 34, wherein said computing means generates said initialization status signal in response to storing said selected data, said fixed pattern data, and said checksum.

Claim 39

The apparatus of claim 35, wherein said computing means, in response to said reset signal, verifies the validity of said stored fixed pattern data by comparing said stored fixed pattern data to said fixed pattern data.

Claim 40

The apparatus of claim 36, wherein said computing means clears said stored selected data, said stored fixed pattern data, and said stored checksum from said memory storage device in response to detecting corruption of said stored fixed pattern data.

Claim 41

The apparatus of claim 37, wherein said computing means executes an initial instruction set and builds new operating data in response to clearing said stored selected data, said stored fixed pattern data, and said stored checksum.

Claim 42

The apparatus of claim 36, wherein said computing means verifies the validity of said stored checksum in response to verifying that said fixed pattern data is valid, by calculating the sum of said stored selected data and said stored fixed pattern data to produce a new checksum and comparing said new checksum to said stored checksum.

Claim 43

The apparatus of claim 39, wherein said computing means clears said stored selected data, said stored fixed pattern data, and said stored checksum from said memory storage device in response to detecting corruption of said stored checksum.

Claim 44

The apparatus of claim 40, wherein said computing means executes an initial instruction set and builds new operating data in response to clearing said stored selected data, said stored fixed pattern data, and said stored checksum.

Claim 45

The apparatus of claim 39, wherein said computing means clears said stored fixed pattern data and all of said operating data, other than said stored selected data, from said memory storage device in response to verifying that said stored checksum is valid.

Claim 46

The apparatus of claim 42, wherein said computing means executes an initial instruction set upon said selected stored data in response to clearing said stored fixed pattern data and said all data.

Claim 47

The apparatus of claim 31, wherein said computing means is a microprocessor.

Claim 48

The apparatus of claim 31, wherein said memory storage means is random access memory (RAM).

Claim 49

The apparatus of claim 45, wherein said RAM is external to said computing means.

Claim 50

The apparatus of claim 45, wherein said RAM is internal to said computing means.

Claim 51

The apparatus of claim 31, wherein said first timing means is external to said computing means.

Claim 52

The apparatus of claim 48, wherein said initialization means is external to said computing means.

Claim 53

The apparatus of claim 31, wherein said first timing means is internal to said computing means.

Claim 54

The apparatus of claim 31, wherein each of said first time interval and said second time interval is a fixed time period.

Claim 55

The apparatus of claim 31, wherein each of said first time interval and said second time interval is a variable time interval.

Claim 58

The method of claim 53, including the step of completing current processing of operating data and causing the storage of a selected set of said operating data and fixed pattern data to provide stored selected data and stored fixed pattern data in response to said first signal and within said second time interval.

Claim 59

The method of claim 54, including the step of calculating a checksum, representative of the sum of said stored selected data and said stored fixed pattern data, in response to said first signal and within said second time interval.

Claim 60

The method of claim 55, including the step of storing said checksum to provide a stored checksum in response to said first signal and within said second time interval.

Claim 61

The method of claim 56, including the step of verifying the validity of said stored fixed pattern data, in response to said second signal, by comparing said stored fixed pattern data to said fixed pattern data.

Claim 62

The method of claim 57, including the step of clearing said stored selected data, said stored fixed pattern data, and said stored checksum in response to detecting corruption of said stored fixed pattern data.

Claim 63

The method of claim 58, including the step of executing an initial instruction set and building new operating data in response to clearing of said stored selected data, said stored fixed pattern data, and said stored checksum.

Claim 64

The method of claim 57, including the step of verifying said stored checksum, in response to verifying that said fixed pattern data is valid, by calculating the sum of said stored selected data and said stored fixed pattern data to produce a new checksum and comparing said new checksum to said stored checksum.

Claim 65

The method of claim 60, including the step of clearing said stored selected data, said stored fixed pattern data, and said stored checksum in response to detecting corruption of said stored checksum.

Claim 66

The method of claim 61, including the step of executing an initial instruction set and building new operating data after said said step of clearing said stored selected data, said stored fixed pattern data, and said stored checksum.

Claim 67

The method of claim 60, including the step of clearing said stored fixed pattern data in response to verifying that said stored checksum is valid.

Claim 68

The method of claim 63, including the step of clearing all of said data, other than said stored selected data, and said stored fixed pattern data in response to verifying that said stored checksum is valid.

Claim 69

The method of claim 64, including the step of executing an initial instruction set upon said selected stored data in response to clearing said all data other than said stored selected data, and said stored fixed pattern data.