Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
335 words
A microcomputer system, comprising: (a) an abnormal state display means, (b) a microcomputer comprising: (i) a microprocessor means, and (ii) a system clock means for producing system clock signals, (c) a watchdog timer circuit external to the microcomputer comprising: (i) a timer clock, different from said system clock means, for producing timer clock signals, (ii) a counter means for receiving and counting said timer clock signals, and upon reaching a first predetermined count indicating passage of a first time interval since reset of said watchdog timer circuit, causing forcible reset of said microprocessor means, (d) a timer circuit means including a counter receiving and counting said system clock signals, and upon reaching a second predetermined count indicating passage of a second time interval since reset of said timer circuit means, causing one of (i) forcible resetting of said microprocessor means and (ii) activation of said abnormal state display means, (e) said microprocessor means comprising means for: (i) detecting, in cooperation with said timer circuit means, whether an abnormal condition exists in said watchdog timer circuit and generating an abnormal condition signal in response to a detection of an abnormal condition, (ii) causing a reset output signal to be supplied to said counter means of said watchdog timer circuit prior to said counter means reaching said first predetermined count, unless a said abnormal condition signal has been generated, (iii) in response to occurrence of each of said timer clock signals of said watchdog timer circuit, supplying repeated reset output signals to said counter of said timer circuit means to reset said timer circuit means to prevent its counter from reaching said second predetermined count, and (iv) stopping supplying of said repeated reset output signal to said counter of said timer circuit means in response to detection of said abnormal condition existing in said watchdog timer circuit, said counter of said timer circuit means reaching said second predetermined count in an absence of receipt of one of said repeated reset output signals during said second time interval.
Claim 2
Dependent Claim
335 words
A microcomputer system, comprising: (a) an abnormal state display means, (b) a microcomputer comprising: (i) a microprocessor means, and (ii) a system clock means for producing system clock signals, (c) a watchdog timer circuit external to the microcomputer comprising: (i) a timer clock, different from said system clock means, for producing timer clock signals, (ii) a counter means for receiving and counting said timer clock signals, and upon reaching a first predetermined count indicating passage of a first time interval since reset of said watchdog timer circuit, causing forcible reset of said microprocessor means, (d) a timer circuit means including a counter receiving and counting said system clock signals, and upon reaching a second predetermined count indicating passage of a second time interval since reset of said timer circuit means, causing one of (i) forcible resetting of said microprocessor means and (ii) activation of said abnormal state display means, (e) said microprocessor means comprising means for: (i) detecting, in cooperation with said timer circuit means, whether an abnormal condition exists in said watchdog timer circuit and generating an abnormal condition signal in response to a detection of an abnormal condition, (ii) causing a reset output signal to be supplied to said counter means of said watchdog timer circuit prior to said counter means reaching said first predetermined count, unless a said abnormal condition signal has been generated, (iii) in response to occurrence of each of said timer clock signals of said watchdog timer circuit, supplying repeated reset output signals to said counter of said timer circuit means to reset said timer circuit means to prevent its counter from reaching said second predetermined count, and (iv) stopping supplying of said repeated reset output signal to said counter of said timer circuit means in response to detection of said abnormal condition existing in said watchdog timer circuit, said counter of said timer circuit means reaching said second predetermined count in an absence of receipt of one of said repeated reset output signals during said second time interval.
Claim 3
Dependent Claim
51 words
The microcomputer system as in claim 1, wherein said microprocessor means comprises means, responsive to an interruption in occurrence of said timer clock signals from said timer clock of said watchdog timer circuit, for providing a signal causing activation of said abnormal state display means and reset of said microprocessor means.