Test carrier for attaching a semiconductor device

Claim 1

A semiconductor device test carrier comprising: a printed circuit board (CB) substrate having a top surface, a bottom surface, and periphery; a rectangular cavity centrally located on said top surface and extending through to said bottom surface; said cavity is concentric within a conductive ground trace patternly provided on the top surface of said PCB substrate; conductive corner power traces are provided adjacent each corner of said ground trace, and a ruled pattern of conductive wire bond fingers encircling said corner power traces are also provided in a linear array on each of four sides encircling said power traces; a first interstitial ball pad array encircling said conductive wire bond pads connects the bottom surface by way of conductive vias and communicates with a second interstitial ball pad array at the bottom surface; a glass plate fitted and bonded to the underside of said PCB substrate forms a transparent bottom supporting surface for said rectangular cavity; a semiconductor device with its backside bonded to said glass substrate within said cavity, bares both front and back sides of said device for EMMI failure analysis.

Claim 15

A method for forming a semiconductor device test carrier using a printed circuit board (PCB) comprising the steps of providing an off-the-shelf PCB to be modified to receive a semiconductor device, said PCB having a top surface, a bottom surface and periphery; machining a rectangular cavity centrally located on the top surface and extending through to the bottom surface, said rectangular cavity is positioned concentric and within a conductive ground trace patternly formed on the top surface of said PCB, with conductive corner power traces patternly formed adjacent each corner of said ground trace, and providing a ruling pattern of conductive wire bond pads encircling the corner power traces, said wire bond pads formed in a linear array on each of four sides encircling the power trace, and providing a first interstitial ball pad array encircling the conductive wire bond pads for connecting with the bottom surface by way of conductive vias communicating with a second interstitial ball pad array at the bottom surface, whereas each of said conductive wire bond fingers comprising said ruling pattern have conductive traces connected to said first pattern of ball pads to establish electrical communication between said conductive wire bond fingers and said first pattern of ball pads; providing and attaching a glass plate, with an adhesive, to the underside of the insulated substrate to form a transparent bottom supporting surface for the rectangular cavity; providing a semiconductor device having a front side, a back side and periphery; placing said device into cavity of said substrate and adhesively bonding its backside to the glass plate thereby baring both backside and frontside for EMMI failure analysis, said device showing a plurality of bonding pads on its front side which serve as input/output terminals for said device; providing conductive wire and wire bonder for connecting said bonding pads of said device to appropriate wire bond fingers and traces of said substrate; and providing an encapsulate for encapsulating all wire connections between said device and said device test carrier.

Claim 16

A method for forming a semiconductor device test carrier using a printed circuit board (PCB) comprising the steps of providing an off-the-shelf PCB to be modified to receive a semiconductor device, said PCB having a top surface, a bottom surface and periphery; machining a rectangular cavity centrally located on the top surface and extending through to the bottom surface, said rectangular cavity is positioned concentric and within a conductive ground trace patternly formed on the top surface of said PCB, with conductive corner power traces patternly formed adjacent each corner of said ground trace, and providing a ruling pattern of conductive wire bond pads encircling the corner power traces, said wire bond pads formed in a linear array on each of four sides encircling the power trace, and providing a first interstitial ball pad array encircling the conductive wire bond pads for connecting with the bottom surface by way of conductive vias communicating with a second interstitial ball pad array at the bottom surface, whereas each of said conductive wire bond fingers comprising said ruling pattern have conductive traces connected to said first pattern of ball pads to establish electrical communication between said conductive wire bond fingers and said first pattern of ball pads; providing and attaching a glass plate, with an adhesive, to the underside of the insulated substrate to form a transparent bottom supporting surface for the rectangular cavity; providing a semiconductor device having a front side, a back side and periphery; placing said device into cavity of said substrate and adhesively bonding its backside to the glass plate thereby baring both backside and frontside for EMMI failure analysis, said device showing a plurality of bonding pads on its front side which serve as input/output terminals for said device; providing conductive wire and wire bonder for connecting said bonding pads of said device to appropriate wire bond fingers and traces of said substrate; and providing an encapsulate for encapsulating all wire connections between said device and said device test carrier.