Patent US6119241A successfully refreshed from Google Patents.
US6119241A
Expired / Lapsed
US
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Self regulating temperature/performance/voltage scheme for micros (X86)
Assignee: Marvell International Ltd
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Filing: 1998-10-30
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Granted: 2000-09-12
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Expires: 2018-10-30
Abstract
Abstract A processor which optimizes performance opportunistically by using a hierarchy of variables comprising voltage, clocking and the operations being performed by the processor or its system. The invention accomplishes performance optimization by defining various states with the goal that the processor stays in an optimal performance state of accelerated voltage and clock when the processor executional units are operating. The states are selected by a logic network based on information that is provided by temperature sensors and a performance control. The logic network can be envisioned as an UP-DOWN counter. The counter can be advanced UP or DOWN the state "ladder" as the conditions warrant.
Inventors
- 👤 Michel Salib Michail
- 👤 Wilbur David Pricer
- 👤 Sebastian Theodore Ventrone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 22:25
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; G06F1/04; G06F1/08; G06F1/16; G06F1/20; G06F1/206; G06F1/3296; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
89 words
A processor having a control block which comprises: a logic circuit which receives inputs from the processor's operational unit and a temperature sensing unit, the logic circuit comprising logic for determining a plurality of voltage states and clock states; a utilization control which manages the performance of the operational units based on outputs from the logic circuit; clock generation circuits providing for the clock states; and voltage generation circuits providing for the voltage states, the clock generation circuits and voltage generation circuits responsive to outputs from the logic circuit.
Claim 2
Dependent Claim
89 words
A processor having a control block which comprises: a logic circuit which receives inputs from the processor's operational unit and a temperature sensing unit, the logic circuit comprising logic for determining a plurality of voltage states and clock states; a utilization control which manages the performance of the operational units based on outputs from the logic circuit; clock generation circuits providing for the clock states; and voltage generation circuits providing for the voltage states, the clock generation circuits and voltage generation circuits responsive to outputs from the logic circuit.
Claim 3
Dependent Claim
18 words
The control block of claim 1, wherein the logic circuit is in the form of an up-down counter.
Claim 4
Dependent Claim
26 words
The control block of claim 2, wherein the up-down counter is constructed so that an advancing up or down can only occur on clock cycle boundaries.
Claim 5
Dependent Claim
16 words
The control block of claim 1, wherein the temperature sensing unit comprises of temperature sensitive diodes.
Claim 6
Dependent Claim
22 words
The control block of claim 1, wherein the logic circuit provides for a reduced clock, a normal clock and an accelerated clock.
Claim 7
Dependent Claim
19 words
The control block of claim 5, wherein the logic circuit provides for a normal voltage and an accelerated voltage.
Claim 8
Independent Claim
78 words
A method for optimizing processor performance comprising the steps of switching to an accelerated clock and voltage state when a temperature sensed in the processor is under a temperature Topt; placing the utilization control over the processor's functional units when the temperature exceeds the temperature Topt; switching to a normal clock state and a normal voltage state when the temperature sensed in the processor exceeds a temperature Tswitch, wherein the temperature Tswitch is higher than the temperature Topt.
Claim 9
Independent Claim
78 words
A method for optimizing processor performance comprising the steps of switching to an accelerated clock and voltage state when a temperature sensed in the processor is under a temperature Topt; placing the utilization control over the processor's functional units when the temperature exceeds the temperature Topt; switching to a normal clock state and a normal voltage state when the temperature sensed in the processor exceeds a temperature Tswitch, wherein the temperature Tswitch is higher than the temperature Topt.
Claim 10
Dependent Claim
25 words
The method of claim 7 also comprising the step of moving to a reduced clock state when the processor detects a string of NO-OP instructions.
Claim 11
Dependent Claim
26 words
The method of claim 8 also comprising the step of moving to a normal voltage and normal clock state whenever the processor detects bus activity only.
Claim 12
Dependent Claim
28 words
The method of claim 7 also comprising the step of transitioning from a normal voltage stage to an accelerated voltage state before moving to an accelerated clock state.
Claim 13
Dependent Claim
26 words
The method of claim 7 also comprising the step of transitioning to a normal clock prior to moving from an accelerated voltage to a normal voltage.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-12 | 2004-03-13 | 2004-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-12 | 2008-03-13 | 2008-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-12 | 2012-03-13 | 2012-09-12 | $7700.00 | Window Closed / Lapsed |