Integration of a salicide process for MOS logic devices, and a self-aligned contact process for MOS memory devices

Claim 1

A method of fabricating MOS memory devices, and MOS logic devices on a single semiconductor substrate, comprising the steps of: forming silicon nitride capped, polycide gate structures, on a first gate insulator layer, on a first region of said semiconductor substrate, to be used for said MOS memory devices; forming first lightly doped source/drain regions, in an area of said first region of said semiconductor substrate, not covered by said silicon nitride capped, polycide gate structures; forming first insulator spacers on the sides of said silicon nitride capped, polycide gate structures; depositing a first interlevel planarization, (IPO), layer; forming self-aligned contact, (SAC), openings, in said first IPO layer, located in said first region of said semiconductor substrate, exposing said first lightly doped source/drain regions, located between said silicon nitride capped, polycide gate structures; forming a first polysilicon plug structure, in a first SAC opening, and forming a second polysilicon plug structure, in a second SAC opening; removing said first IPO layer, from said second region of said semiconductor substrate; forming polysilicon gate structures, on a second gate insulator layer, on a second region of said semiconductor substrate, to be used for said MOS logic devices; forming second lightly doped source/drain regions, in an area of said second region of said semiconductor substrate, not covered by said polysilicon gate structures; forming second insulator spacers on the sides of said polysilicon gate structures; forming heavily doped source/drain regions, in an area of said second region of said semiconductor substrate, not covered by said polysilicon gate structures, and not covered by said second insulator spacers; performing a rapid thermal anneal procedure; forming a protective insulator layer, in said first region of said semiconductor substrate, overlying the top surface of the polysilicon plug structures; selectively forming a metal silicide layer on the top surface of said polysilicon gate structures, and on the top surface of said heavily doped source/drain regions; depositing a second IPO layer; forming a bit line opening, in said second IPO layer, and in said protective insulator layer, exposing a portion of the top surface of said first polysilicon plug structure, and forming a storage node opening in said second IPO layer, and in said protective insulator layer, exposing a portion of the top surface of said second polysilicon plug structure; forming a bit line structure in said bit line opening, and forming a storage node contact structure, in said storage node opening; depositing a third IPO layer; forming a capacitor opening, in said third IPO layer, exposing the top surface of said storage node contact structure; and forming a capacitor structure in said capacitor opening.

Claim 2

A method of fabricating MOS memory devices, and MOS logic devices on a single semiconductor substrate, comprising the steps of: forming silicon nitride capped, polycide gate structures, on a first gate insulator layer, on a first region of said semiconductor substrate, to be used for said MOS memory devices; forming first lightly doped source/drain regions, in an area of said first region of said semiconductor substrate, not covered by said silicon nitride capped, polycide gate structures; forming first insulator spacers on the sides of said silicon nitride capped, polycide gate structures; depositing a first interlevel planarization, (IPO), layer; forming self-aligned contact, (SAC), openings, in said first IPO layer, located in said first region of said semiconductor substrate, exposing said first lightly doped source/drain regions, located between said silicon nitride capped, polycide gate structures; forming a first polysilicon plug structure, in a first SAC opening, and forming a second polysilicon plug structure, in a second SAC opening; removing said first IPO layer, from said second region of said semiconductor substrate; forming polysilicon gate structures, on a second gate insulator layer, on a second region of said semiconductor substrate, to be used for said MOS logic devices; forming second lightly doped source/drain regions, in an area of said second region of said semiconductor substrate, not covered by said polysilicon gate structures; forming second insulator spacers on the sides of said polysilicon gate structures; forming heavily doped source/drain regions, in an area of said second region of said semiconductor substrate, not covered by said polysilicon gate structures, and not covered by said second insulator spacers; performing a rapid thermal anneal procedure; forming a protective insulator layer, in said first region of said semiconductor substrate, overlying the top surface of the polysilicon plug structures; selectively forming a metal silicide layer on the top surface of said polysilicon gate structures, and on the top surface of said heavily doped source/drain regions; depositing a second IPO layer; forming a bit line opening, in said second IPO layer, and in said protective insulator layer, exposing a portion of the top surface of said first polysilicon plug structure, and forming a storage node opening in said second IPO layer, and in said protective insulator layer, exposing a portion of the top surface of said second polysilicon plug structure; forming a bit line structure in said bit line opening, and forming a storage node contact structure, in said storage node opening; depositing a third IPO layer; forming a capacitor opening, in said third IPO layer, exposing the top surface of said storage node contact structure; and forming a capacitor structure in said capacitor opening.

Claim 17

A method of fabricating MOS memory, and MOS logic devices, on a single semiconductor substrate, with said MOS memory devices, featuring polycide gate structures, with first insulator sidewall spacers, on a second gate insulator layer, and with self-aligned contact openings, and with said MOS logic devices featuring, metal silicide-polysilicon gate structures, with second insulator sidewall spacers, on a first gate insulator layer, comprising the steps of: forming isolation regions in said semiconductor substrate; growing said first gate insulator layer on a region of semiconductor substrate to be used for said MOS logic devices; forming a first polysilicon layer, on said first gate insulator layer, in the MOS logic region; forming a first silicon oxide layer on said first polysilicon layer, in said MOS logic region; growing a second gate insulator layer, thicker than said first gate insulator layer, on the region of said semiconductor substrate to be used for said MOS memory devices; depositing a second polysilicon layer; depositing a tungsten silicide layer; depositing a thin silicon oxide layer; depositing a capping silicon nitride layer; performing an anisotropic RIE procedure to create silicon nitride capped, polycide gate structures, on said second gate insulator layer, in said MOS memory region, with said polycide gate structures, comprised of said tungsten silicide layer, on said second polysilicon layer, with said anisotropic RIE procedure completely removing said capping silicon nitride layer, said thin silicon oxide layer, said tungsten silicide layer, and said second polysilicon layer, from said first silicon oxide layer, in said MOS logic region; forming first lightly doped source/drain regions, in a area of said MOS memory region, not covered by said silicon nitride capped, polycide gate structures; forming said first insulator sidewall spacers, comprised of silicon nitride, on the sides of said silicon nitride capped, polycide gate structures; depositing a first IPO layer; forming said SAC openings, in said first IPO layer, between said silicon nitride capped, polycide gate structures located in said MOS memory region, with said SAC openings comprised with a width greater than the space between said silicon nitride capped, polycide gate structures, exposing said first lightly doped source/drain regions; forming polysilicon plug structures, in said SAC openings; removing the portion of said first IPO layer residing in said MOS logic region, and removing said first silicon oxide layer from said first polysilicon layer; forming polysilicon gate structures, on said first gate insulator layer, in said MOS logic region; forming second lightly doped source/drain regions, in said MOS logic region, in an area of said semiconductor substrate, not covered by said polysilicon gate structures; forming said second insulator sidewall spacers on the sides of said polysilicon gate structures, with said second insulator sidewall spacers, thicker than said first insulator sidewall spacers, located on the sides of said silicon nitride capped, polycide gate structures, in said MOS memory region; forming heavily doped source/drain regions, in said MOS logic region, in an area of said semiconductor substrate not covered by said polysilicon gate structures, and not covered by said second insulator sidewall spacers; performing an RTA procedure; forming a protective silicon oxide layer on said first IPO layer, and on the top surface of said polysilicon plug structures, in said MOS memory regions; forming a metal silicide layer on the top surface of said polysilicon gate structures, and on the top surface of said heavily doped source/drain regions, in said MOS logic region; depositing a second IPO layer; forming a bit line opening in said second IPO layer, and in said protective silicon oxide layer, exposing the top surface of a first polysilicon plug structure, and opening a storage node contact hole, in said second IPO layer, and in said protective silicon oxide layer, exposing the top surface of a second polysilicon plug structure; depositing a third polysilicon layer, completely filling said bit line opening, and completely filling said storage node contact hole; removing regions of said third polysilicon layer from the top surface of said second IPO layer, creating a polysilicon bit line structure, in said bit line opening, and creating a polysilicon storage node contact structure, in said storage node contact hole; depositing a third IPO layer; forming a capacitor opening in said third IPO layer, exposing the top surface of said polysilicon storage node contact structure; forming a polysilicon storage node structure, in said capacitor opening; forming a capacitor dielectric layer, on said polysilicon storage node structure; and forming a polysilicon upper electrode structure, on said capacitor dielectric layer.

Claim 18

A method of fabricating MOS memory, and MOS logic devices, on a single semiconductor substrate, with said MOS memory devices, featuring polycide gate structures, with first insulator sidewall spacers, on a second gate insulator layer, and with self-aligned contact openings, and with said MOS logic devices featuring, metal silicide-polysilicon gate structures, with second insulator sidewall spacers, on a first gate insulator layer, comprising the steps of: forming isolation regions in said semiconductor substrate; growing said first gate insulator layer on a region of semiconductor substrate to be used for said MOS logic devices; forming a first polysilicon layer, on said first gate insulator layer, in the MOS logic region; forming a first silicon oxide layer on said first polysilicon layer, in said MOS logic region; growing a second gate insulator layer, thicker than said first gate insulator layer, on the region of said semiconductor substrate to be used for said MOS memory devices; depositing a second polysilicon layer; depositing a tungsten silicide layer; depositing a thin silicon oxide layer; depositing a capping silicon nitride layer; performing an anisotropic RIE procedure to create silicon nitride capped, polycide gate structures, on said second gate insulator layer, in said MOS memory region, with said polycide gate structures, comprised of said tungsten silicide layer, on said second polysilicon layer, with said anisotropic RIE procedure completely removing said capping silicon nitride layer, said thin silicon oxide layer, said tungsten silicide layer, and said second polysilicon layer, from said first silicon oxide layer, in said MOS logic region; forming first lightly doped source/drain regions, in a area of said MOS memory region, not covered by said silicon nitride capped, polycide gate structures; forming said first insulator sidewall spacers, comprised of silicon nitride, on the sides of said silicon nitride capped, polycide gate structures; depositing a first IPO layer; forming said SAC openings, in said first IPO layer, between said silicon nitride capped, polycide gate structures located in said MOS memory region, with said SAC openings comprised with a width greater than the space between said silicon nitride capped, polycide gate structures, exposing said first lightly doped source/drain regions; forming polysilicon plug structures, in said SAC openings; removing the portion of said first IPO layer residing in said MOS logic region, and removing said first silicon oxide layer from said first polysilicon layer; forming polysilicon gate structures, on said first gate insulator layer, in said MOS logic region; forming second lightly doped source/drain regions, in said MOS logic region, in an area of said semiconductor substrate, not covered by said polysilicon gate structures; forming said second insulator sidewall spacers on the sides of said polysilicon gate structures, with said second insulator sidewall spacers, thicker than said first insulator sidewall spacers, located on the sides of said silicon nitride capped, polycide gate structures, in said MOS memory region; forming heavily doped source/drain regions, in said MOS logic region, in an area of said semiconductor substrate not covered by said polysilicon gate structures, and not covered by said second insulator sidewall spacers; performing an RTA procedure; forming a protective silicon oxide layer on said first IPO layer, and on the top surface of said polysilicon plug structures, in said MOS memory regions; forming a metal silicide layer on the top surface of said polysilicon gate structures, and on the top surface of said heavily doped source/drain regions, in said MOS logic region; depositing a second IPO layer; forming a bit line opening in said second IPO layer, and in said protective silicon oxide layer, exposing the top surface of a first polysilicon plug structure, and opening a storage node contact hole, in said second IPO layer, and in said protective silicon oxide layer, exposing the top surface of a second polysilicon plug structure; depositing a third polysilicon layer, completely filling said bit line opening, and completely filling said storage node contact hole; removing regions of said third polysilicon layer from the top surface of said second IPO layer, creating a polysilicon bit line structure, in said bit line opening, and creating a polysilicon storage node contact structure, in said storage node contact hole; depositing a third IPO layer; forming a capacitor opening in said third IPO layer, exposing the top surface of said polysilicon storage node contact structure; forming a polysilicon storage node structure, in said capacitor opening; forming a capacitor dielectric layer, on said polysilicon storage node structure; and forming a polysilicon upper electrode structure, on said capacitor dielectric layer.