Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC)

Claim 1

A method for making improved gate electrodes and sidewall spacers for field effect transistors (FETs) having self-aligned contacts (SAC) comprising the steps of: providing a semiconductor substrate having device areas; forming a gate oxide on said device areas; depositing a polysilicon layer on said device areas and elsewhere on said substrate, said polysilicon layer being conductively doped; depositing a first insulating layer on said polysilicon layer; depositing a hard mask layer on said first insulating layer; patterning by using a photoresist mask and anisotropic plasma etching said hard mask, said first insulating layer, and said first polysilicon layer, thereby forming stacked gate electrode structures having vertical sidewalls over said device areas; forming by ion implantation lightly doped source/drain areas in said device areas adjacent to said gate electrode structures; growing by thermal oxidation a polysilicon oxide layer on sidewalls of said polysilicon layer in said stacked gate electrode structures and concurrently on said lightly doped source/drain areas; depositing a conformal first silicon nitride layer over said stacked gate electrode structures; depositing a conformal second insulating layer on said first silicon nitride layer; anisotropically plasma etching said second insulating layer and said first silicon nitride layer thereby forming insulating sidewall spacers on said sidewalls of said stacked gate electrode structures wherein said first silicon nitride layer remaining in said sidewall spacers is contiguous with said hard mask layer; forming source/drain contact areas in said device areas adjacent to said insulating sidewall spacers by ion implanting into said substrate; depositing a blanket conformal second silicon nitride layer; depositing a third insulating layer and annealing to form an essentially planar surface; photoresist masking and selectively wet etching in said third insulating layer to said second silicon nitride layer to form openings extending partially over said stacked gate electrode structures, thereby forming self-aligned source/drain contact openings over said source/drain contact areas; plasma etching said second silicon nitride layer in said source/drain contact openings to said polysilicon oxide layer formed on said source/drain contact areas; performing a pre-metal wet-etch dip to remove said polysilicon oxide thereby exposing said source/drain contact areas; depositing and patterning a metal layer to form electrical contacts to said source/drain contact areas thereby completing said field effect transistors.

Claim 2

A method for making improved gate electrodes and sidewall spacers for field effect transistors (FETs) having self-aligned contacts (SAC) comprising the steps of: providing a semiconductor substrate having device areas; forming a gate oxide on said device areas; depositing a polysilicon layer on said device areas and elsewhere on said substrate, said polysilicon layer being conductively doped; depositing a first insulating layer on said polysilicon layer; depositing a hard mask layer on said first insulating layer; patterning by using a photoresist mask and anisotropic plasma etching said hard mask, said first insulating layer, and said first polysilicon layer, thereby forming stacked gate electrode structures having vertical sidewalls over said device areas; forming by ion implantation lightly doped source/drain areas in said device areas adjacent to said gate electrode structures; growing by thermal oxidation a polysilicon oxide layer on sidewalls of said polysilicon layer in said stacked gate electrode structures and concurrently on said lightly doped source/drain areas; depositing a conformal first silicon nitride layer over said stacked gate electrode structures; depositing a conformal second insulating layer on said first silicon nitride layer; anisotropically plasma etching said second insulating layer and said first silicon nitride layer thereby forming insulating sidewall spacers on said sidewalls of said stacked gate electrode structures wherein said first silicon nitride layer remaining in said sidewall spacers is contiguous with said hard mask layer; forming source/drain contact areas in said device areas adjacent to said insulating sidewall spacers by ion implanting into said substrate; depositing a blanket conformal second silicon nitride layer; depositing a third insulating layer and annealing to form an essentially planar surface; photoresist masking and selectively wet etching in said third insulating layer to said second silicon nitride layer to form openings extending partially over said stacked gate electrode structures, thereby forming self-aligned source/drain contact openings over said source/drain contact areas; plasma etching said second silicon nitride layer in said source/drain contact openings to said polysilicon oxide layer formed on said source/drain contact areas; performing a pre-metal wet-etch dip to remove said polysilicon oxide thereby exposing said source/drain contact areas; depositing and patterning a metal layer to form electrical contacts to said source/drain contact areas thereby completing said field effect transistors.

Claim 15

A method for making improved gate electrodes and sidewall spacers for field effect transistors (FETS) having self-aligned contacts (SAC) comprising the steps of: providing a semiconductor substrate having device areas; forming a gate oxide on said device areas; depositing a polysilicon layer on said device areas and elsewhere on said substrate, said polysilicon layer being conductively doped; depositing on said polysilicon layer a first insulating layer composed of a silicon oxide deposited by chemical vapor deposition (CVD) using reactant gas tetraethosiloxane (TEOS); depositing a hard mask layer composed of silicon nitride on said first insulating layer; patterning by using a photoresist mask and anisotropic plasma etching said hard mask, said first insulating layer, and said polysilicon layer, thereby forming stacked gate electrode structures having vertical sidewalls over said device areas; forming by ion implantation lightly doped source/drain areas in said device areas adjacent to said gate electrode structures; growing by thermal oxidation a polysilicon oxide layer on sidewalls of said polysilicon layer in said stacked gate electrode structures and concurrently on said lightly doped source/drain areas; depositing a conformal first silicon nitride layer over said stacked gate electrode structures; depositing a conformal second insulating layer on said first silicon nitride layer; anisotropically plasma etching said second insulating layer and said first silicon nitride layer thereby forming insulating sidewall spacers on said sidewalls of said stacked gate electrode structures wherein said first silicon nitride layer remaining in said sidewall spacers is contiguous with said hard mask layer; forming source/drain contact areas in said device areas adjacent to said insulating sidewall spacers by ion implanting into said substrate; depositing a blanket conformal second silicon nitride layer; depositing a third insulating layer and annealing to form an essentially planar surface; photoresist masking and selectively wet etching in said third insulating layer to said second silicon nitride layer to form openings extending partially over said stacked gate electrode structures, thereby forming self-aligned source/drain contact openings over said source/drain contact areas; plasma etching said second silicon nitride layer in said source/drain contact openings to said polysilicon oxide layer formed on said source/drain contact areas; performing a pre-metal wet-etch dip to remove said polysilicon oxide thereby exposing said source/drain contact areas; depositing and patterning a metal layer to form electrical contacts to said source/drain contact areas thereby completing said field effect transistors.

Claim 16

A method for making improved gate electrodes and sidewall spacers for field effect transistors (FETS) having self-aligned contacts (SAC) comprising the steps of: providing a semiconductor substrate having device areas; forming a gate oxide on said device areas; depositing a polysilicon layer on said device areas and elsewhere on said substrate, said polysilicon layer being conductively doped; depositing on said polysilicon layer a first insulating layer composed of a silicon oxide deposited by chemical vapor deposition (CVD) using reactant gas tetraethosiloxane (TEOS); depositing a hard mask layer composed of silicon nitride on said first insulating layer; patterning by using a photoresist mask and anisotropic plasma etching said hard mask, said first insulating layer, and said polysilicon layer, thereby forming stacked gate electrode structures having vertical sidewalls over said device areas; forming by ion implantation lightly doped source/drain areas in said device areas adjacent to said gate electrode structures; growing by thermal oxidation a polysilicon oxide layer on sidewalls of said polysilicon layer in said stacked gate electrode structures and concurrently on said lightly doped source/drain areas; depositing a conformal first silicon nitride layer over said stacked gate electrode structures; depositing a conformal second insulating layer on said first silicon nitride layer; anisotropically plasma etching said second insulating layer and said first silicon nitride layer thereby forming insulating sidewall spacers on said sidewalls of said stacked gate electrode structures wherein said first silicon nitride layer remaining in said sidewall spacers is contiguous with said hard mask layer; forming source/drain contact areas in said device areas adjacent to said insulating sidewall spacers by ion implanting into said substrate; depositing a blanket conformal second silicon nitride layer; depositing a third insulating layer and annealing to form an essentially planar surface; photoresist masking and selectively wet etching in said third insulating layer to said second silicon nitride layer to form openings extending partially over said stacked gate electrode structures, thereby forming self-aligned source/drain contact openings over said source/drain contact areas; plasma etching said second silicon nitride layer in said source/drain contact openings to said polysilicon oxide layer formed on said source/drain contact areas; performing a pre-metal wet-etch dip to remove said polysilicon oxide thereby exposing said source/drain contact areas; depositing and patterning a metal layer to form electrical contacts to said source/drain contact areas thereby completing said field effect transistors.