Self-aligned contact process

Claim 1

A method of forming a self-aligned contact on a device including a semiconductor substrate comprising the steps as follows: forming a gate oxide layer on said substrate, forming a gate electrode layer on said gate oxide layer, forming a stacked dielectric structure stacked on said gate electrode layer, and then patterning said stacked dielectric structure and said gate electrode layer to form a stacked gate electrode, forming a dielectric layer blanketing said device, forming a first mask over said dielectric layer, said first mask covering a masked region, and then etching said dielectric layer through said mask to form a self-aligned contact opening into said dielectric layer leaving a first dielectric spacer adjacent to said stacked gate electrode and leaving said masked region covered by the remainder of said dielectric layer, removing said first mask, depositing a second electrode layer over said dielectric layer having said contact opening, then forming a second mask and patterning said second electrode layer by etching through said second mask, thereby forming a self-aligned contact structure in said opening, and applying an ion implantation process to said self-aligned contact structure in said opening, then the remainder of said dielectric layer is etched away leaving additional spacers adjacent to exposed surfaces of said substrate, and followed by ion implantation of dopant into said substrate through said exposed surfaces.

Claim 2

A method of forming a self-aligned contact on a device including a semiconductor substrate comprising the steps as follows: forming a gate oxide layer on said substrate, forming a gate electrode layer on said gate oxide layer, forming a stacked dielectric structure stacked on said gate electrode layer, and then patterning said stacked dielectric structure and said gate electrode layer to form a stacked gate electrode, forming a dielectric layer blanketing said device, forming a first mask over said dielectric layer, said first mask covering a masked region, and then etching said dielectric layer through said mask to form a self-aligned contact opening into said dielectric layer leaving a first dielectric spacer adjacent to said stacked gate electrode and leaving said masked region covered by the remainder of said dielectric layer, removing said first mask, depositing a second electrode layer over said dielectric layer having said contact opening, then forming a second mask and patterning said second electrode layer by etching through said second mask, thereby forming a self-aligned contact structure in said opening, and applying an ion implantation process to said self-aligned contact structure in said opening, then the remainder of said dielectric layer is etched away leaving additional spacers adjacent to exposed surfaces of said substrate, and followed by ion implantation of dopant into said substrate through said exposed surfaces.