US6008081A
Expired / Lapsed
US
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Method of forming electrostatic discharge protection structure of dynamic random access memory
Assignee: FOOTHILLS IP LLC
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Filing: 1998-07-30
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Granted: 1999-12-28
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Expires: 2018-07-30
Abstract
Abstract A dynamic random access memory's (DRAM's) electrostatic discharge (ESD) protection circuit structure and its method of manufacture, wherein the ESD protection circuit and the capacitors are formed at the same time. The ESD protection circuit has a heavily doped drain structure so that hot carriers can be recruited for discharging electrostatics and a better electrostatic discharge protection can be achieved. Furthermore, no additional electrostatic discharge implant operations are necessary.
Inventors
- 👤 Tsung-Chih Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 12:56
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/09; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10B12/02; H10B12/03; H10B12/033
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
465 words
A method of forming electrostatic discharge protection circuit of dynamic random access memory, the method comprising the steps of: providing a semiconductor substrate, wherein the semiconductor substrate having an isolating structure that separates the substrate into a device region and a protective circuit region, and a first gate structure and a second gate structure are formed in the device region and the protective circuit region, respectively; performing a first ion implantation by implanting ions into the substrate on each side of the first gate structure and the second gate structure to form a lightly doped first source/drain region and a first common source/drain region in the device region and a lightly doped first source/drain region in the protective circuit region; forming first spacers and second spacers over sidewalls of the first gate structure and the second gate structure, respectively; performing a lightly doped first ion implantation by implanting ions into the second source/drain region in the protective circuit region to form a heavily doped first source/drain region; forming a first dielectric layer over an entire substrate; patterning the first dielectric layer to form a first contact opening that exposes the first common source/drain region in the device region, and forming a third gate structure in the protective circuit region; performing a third ion implantation by implanting ions into the first common source/drain region exposed by the first contact opening and the semiconductor substrate on each side of the third gate structure, thereby forming a heavily doped first common source/drain region in the device region, and a heavily doped second source/drain region and a heavily doped first common source/drain region in the protective circuit region; forming third spacers covering sidewalls of the third gate structure and the first dielectric layer; forming a bit line and a resistor that connect to the first common source/drain region exposed by the first contact opening and the heavily doped first common source/drain region, respectively; forming a second dielectric layer over the entire substrate; patterning the second dielectric layer and the first dielectric layer in the device region to form a second contact opening that exposes the lightly doped first source/drain region; forming a lower electrode to connect to the lightly doped first source/drain region exposed through the second contact opening; forming a third dielectric layer and an upper electrode over the lower electrode to complete a capacitor in dynamic random access memory; forming a fourth dielectric layer over the entire substrate; patterning the fourth dielectric layer and the second dielectric layer in the protective circuit region to form a third contact opening and a fourth contact opening that expose the resistor and the heavily doped second source/drain region, respectively; and forming a conductive layer over the entire substrate to connect to the resistor and the heavily doped second source/drain region.
Claim 2
Independent Claim
465 words
A method of forming electrostatic discharge protection circuit of dynamic random access memory, the method comprising the steps of: providing a semiconductor substrate, wherein the semiconductor substrate having an isolating structure that separates the substrate into a device region and a protective circuit region, and a first gate structure and a second gate structure are formed in the device region and the protective circuit region, respectively; performing a first ion implantation by implanting ions into the substrate on each side of the first gate structure and the second gate structure to form a lightly doped first source/drain region and a first common source/drain region in the device region and a lightly doped first source/drain region in the protective circuit region; forming first spacers and second spacers over sidewalls of the first gate structure and the second gate structure, respectively; performing a lightly doped first ion implantation by implanting ions into the second source/drain region in the protective circuit region to form a heavily doped first source/drain region; forming a first dielectric layer over an entire substrate; patterning the first dielectric layer to form a first contact opening that exposes the first common source/drain region in the device region, and forming a third gate structure in the protective circuit region; performing a third ion implantation by implanting ions into the first common source/drain region exposed by the first contact opening and the semiconductor substrate on each side of the third gate structure, thereby forming a heavily doped first common source/drain region in the device region, and a heavily doped second source/drain region and a heavily doped first common source/drain region in the protective circuit region; forming third spacers covering sidewalls of the third gate structure and the first dielectric layer; forming a bit line and a resistor that connect to the first common source/drain region exposed by the first contact opening and the heavily doped first common source/drain region, respectively; forming a second dielectric layer over the entire substrate; patterning the second dielectric layer and the first dielectric layer in the device region to form a second contact opening that exposes the lightly doped first source/drain region; forming a lower electrode to connect to the lightly doped first source/drain region exposed through the second contact opening; forming a third dielectric layer and an upper electrode over the lower electrode to complete a capacitor in dynamic random access memory; forming a fourth dielectric layer over the entire substrate; patterning the fourth dielectric layer and the second dielectric layer in the protective circuit region to form a third contact opening and a fourth contact opening that expose the resistor and the heavily doped second source/drain region, respectively; and forming a conductive layer over the entire substrate to connect to the resistor and the heavily doped second source/drain region.
Claim 3
Dependent Claim
14 words
The method of claim 1, wherein the isolating structure comprises a field oxide layer.
Claim 4
Dependent Claim
22 words
The method of claim 1, wherein the steps of forming the first and second spacers comprises a plasma-enhanced chemical vapor deposition method.
Claim 5
Dependent Claim
20 words
The method of claim 1, wherein the steps of forming the first and second spacers comprises depositing silicon nitride material.
Claim 6
Dependent Claim
23 words
The method of claim 1, wherein the step of forming the bit line and the resistor comprises a low-pressure chemical vapor deposition method.
Claim 7
Dependent Claim
17 words
The method of claim 1, wherein the step of forming the first dielectric layer comprises depositing tetra-ethyl-ortho-silicate.
Claim 8
Dependent Claim
18 words
The method of claim 1, wherein the step of forming the first dielectric layer comprises depositing borophosphosilicate glass.
Claim 9
Dependent Claim
21 words
The method of claim 1, wherein the step of forming the first dielectric layer comprises a low-pressure chemical vapor depositing method.
Claim 10
Dependent Claim
19 words
The method of claim 1, wherein the step of patterning the first dielectric layer comprises a dry etching method.
Claim 11
Dependent Claim
17 words
The method of claim 1, wherein the step of forming the conductive layer comprises depositing tungsten material.
Claim 12
Dependent Claim
19 words
The method of claim 1, wherein the step of forming the conductive layer comprises a chemical vapor deposition method.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 2002-12-27 | 2003-06-28 | 2003-12-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-12-27 | 2007-06-28 | 2007-12-28 | $3760.00 | Window Closed / Lapsed |
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