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US6093590A
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Method of fabricating transistor having a metal gate and a gate dielectric layer with a high dielectric constant
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1999-09-14
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Granted: 2000-07-25
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Expires: 2019-09-14
Abstract
Abstract A method of fabricating a transistor. A first dielectric layer with a high dielectric constant is formed on a substrate. An oxide layer is formed on the first dielectric layer. A silicon nitride layer is formed on the oxide layer. The silicon nitride layer, the oxide layer, and the first dielectric layer are patterned to form a dummy gate structure. A spacer is formed on a sidewall of the dummy gate structure. The spacer and the dummy gate structure together form a dummy gate. An ion implantation step with the dummy gate serving as a mask and a thermal annealing step are performed to form a source region and a drain region on opposite sides of the dummy gate in the substrate. A second dielectric layer is formed next to the spacer. A top surface of the second dielectric layer is approximately level with a top surface of the dummy gate structure. The silicon nitride layer is removed. A nitridation process is performed to convert the oxide layer into a nitride layer. A metal barrier layer is formed over the substrate to cover the second dielectric layer, the spacer, and the nitride layer. A metal layer is formed on the metal barrier layer. A planarization process is performed to remove a portion of the metal layer and the metal barrier layer to form a metal gate. A top surface of the metal gate is level with a top surface of the second dielectric layer.
Inventors
- 👤 Chine-Gie Lou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 20:50
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/01342; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/01344; H10D64/60; H10D64/66; H10D64/68; H10D64/681; H10D64/685; H10D64/691; H10D64/693; H10P; H10P95/00; H10P95/06; H10P95/062; H10D64/017; H10D64/667
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
243 words
A method of fabricating a transistor, comprising: forming a first dielectric layer with a high dielectric constant on a substrate; forming an oxide layer on the first dielectric layer; forming a silicon nitride layer on the oxide layer; patterning the silicon nitride layer, the oxide layer, and the first dielectric layer to form a dummy gate structure; forming a spacer on a sidewall of the dummy gate structure, wherein the spacer and the dummy gate structure together form a dummy gate; performing an ion implantation step with the dummy gate serving as a mask and performing a thermal annealing step to form a source region and a drain region on opposite sides of the dummy gate in the substrate; forming a second dielectric layer next to the spacer, wherein a top surface of the second dielectric layer is approximately level with a top surface of the dummy gate structure; removing the silicon nitride layer of the dummy gate structure; performing a nitridation process to convert the oxide layer into a nitride layer; forming a metal barrier layer over the substrate to cover the second dielectric layer, the spacer, and the nitride layer; forming a metal layer on the metal barrier layer; and performing a planarization process to remove a portion of the metal layer and the metal barrier layer to form a metal gate, wherein a top surface of the metal gate is level with a top surface of the second dielectric layer.
Claim 2
Independent Claim
243 words
A method of fabricating a transistor, comprising: forming a first dielectric layer with a high dielectric constant on a substrate; forming an oxide layer on the first dielectric layer; forming a silicon nitride layer on the oxide layer; patterning the silicon nitride layer, the oxide layer, and the first dielectric layer to form a dummy gate structure; forming a spacer on a sidewall of the dummy gate structure, wherein the spacer and the dummy gate structure together form a dummy gate; performing an ion implantation step with the dummy gate serving as a mask and performing a thermal annealing step to form a source region and a drain region on opposite sides of the dummy gate in the substrate; forming a second dielectric layer next to the spacer, wherein a top surface of the second dielectric layer is approximately level with a top surface of the dummy gate structure; removing the silicon nitride layer of the dummy gate structure; performing a nitridation process to convert the oxide layer into a nitride layer; forming a metal barrier layer over the substrate to cover the second dielectric layer, the spacer, and the nitride layer; forming a metal layer on the metal barrier layer; and performing a planarization process to remove a portion of the metal layer and the metal barrier layer to form a metal gate, wherein a top surface of the metal gate is level with a top surface of the second dielectric layer.
Claim 3
Dependent Claim
20 words
The method of claim 1, wherein the first dielectric layer comprises a tantalum oxide (Ta 2 O 5 ) layer.
Claim 4
Dependent Claim
14 words
The method of claim 1, wherein the oxide layer comprises a high-temperature oxide layer.
Claim 5
Dependent Claim
14 words
The method of claim 1, wherein a material of the spacer comprises silicon oxide.
Claim 6
Dependent Claim
15 words
The method of claim 1, wherein the second dielectric layer comprises a silicon oxide layer.
Claim 7
Dependent Claim
38 words
The method of claim 1, wherein steps of forming the second dielectric layer comprise: forming a third dielectric layer over the substrate to cover the dummy gate; and performing a chemical-mechanical polishing process on the third dielectric layer.
Claim 8
Dependent Claim
15 words
The method of claim 1, wherein the nitridation process is performed in an ammonia environment.
Claim 9
Dependent Claim
16 words
The method of claim 1, wherein a material of the metal barrier layer comprises titanium nitride.
Claim 10
Dependent Claim
14 words
The method of claim 1, wherein a material of the metal layer comprises tungsten.
Claim 11
Independent Claim
262 words
A method of forming a transistor comprising: forming a dielectric layer having a high dielectric constant on a substrate; forming a high-temperature oxide layer on the dielectric layer; forming a silicon nitride layer on the high-temperature oxide layer; patterning the silicon nitride layer, the high-temperature oxide layer, and the dielectric layer to form a dummy gate structure; forming a silicon oxide spacer on a sidewall of the dummy gate structure, wherein the silicon oxide spacer and the dummy gate structure together form a dummy gate; performing an ion implantation step with the dummy gate serving as a mask and a thermal annealing step to form a source region and a drain region on opposite sides of the dummy gate in the substrate; forming a silicon oxide layer next to the silicon oxide spacer, wherein a top surface of the silicon oxide layer is approximately level with a top surface of the dummy gate structure; removing the silicon nitride layer of the dummy gate structure; performing a nitridation process to convert the high-temperature oxide layer into a nitride layer; forming a metal barrier layer cover the silicon oxide layer, the silicon oxide spacer, and the nitride layer; forming a metal layer on the metal barrier layer; and performing a chemical-mechanical polishing step on the metal layer and the metal barrier layer to form a metal gate, wherein the chemical-mechanical polishing step is performed with the silicon oxide layer serving as a polishing stop, and a top surface of the silicon oxide layer is approximately level with a top surface of the metal gate.
Claim 12
Independent Claim
262 words
A method of forming a transistor comprising: forming a dielectric layer having a high dielectric constant on a substrate; forming a high-temperature oxide layer on the dielectric layer; forming a silicon nitride layer on the high-temperature oxide layer; patterning the silicon nitride layer, the high-temperature oxide layer, and the dielectric layer to form a dummy gate structure; forming a silicon oxide spacer on a sidewall of the dummy gate structure, wherein the silicon oxide spacer and the dummy gate structure together form a dummy gate; performing an ion implantation step with the dummy gate serving as a mask and a thermal annealing step to form a source region and a drain region on opposite sides of the dummy gate in the substrate; forming a silicon oxide layer next to the silicon oxide spacer, wherein a top surface of the silicon oxide layer is approximately level with a top surface of the dummy gate structure; removing the silicon nitride layer of the dummy gate structure; performing a nitridation process to convert the high-temperature oxide layer into a nitride layer; forming a metal barrier layer cover the silicon oxide layer, the silicon oxide spacer, and the nitride layer; forming a metal layer on the metal barrier layer; and performing a chemical-mechanical polishing step on the metal layer and the metal barrier layer to form a metal gate, wherein the chemical-mechanical polishing step is performed with the silicon oxide layer serving as a polishing stop, and a top surface of the silicon oxide layer is approximately level with a top surface of the metal gate.
Claim 13
Dependent Claim
19 words
The method of claim 10, wherein the dielectric layer comprises a tantalum oxide (Ta 2 O 5 ) layer.
Claim 14
Dependent Claim
15 words
The method of claim 10, wherein the nitridation process is performed in an ammonia environment.
Claim 15
Dependent Claim
16 words
The method of claim 10, wherein the material of the metal barrier layer comprises titanium nitride.
Claim 16
Dependent Claim
14 words
The method of claim 10, wherein a material of the metal layer comprises tungsten.
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| 3.5 Years (Year 4) | 2003-07-25 | 2004-01-24 | 2004-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-25 | 2008-01-24 | 2008-07-25 | $3760.00 | Window Closed / Lapsed |
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