US6092124A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for accelerating the rendering of images
Assignee: Nvidia Corp
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Filing: 1998-04-17
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Granted: 2000-07-18
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Expires: 2018-04-17
Abstract
Abstract A direct memory access (DMA) circuit which is physically positioned with an input/output device, the DMA circuit storing a first reference value pointing to a data structure which describes a buffer portion of system memory in which data is stored for transfer to the I/O device, a value determining a position within the buffer portion of system memory beginning at which a next sequence of data is to be placed, and a value determining a position within the buffer portion of system memory from which a next sequences of data is to be copied to the I/O device, the DMA circuit including circuitry for reading data from the buffer portion of system memory beginning at the position from which a next sequences of data is to be copied and for writing the data read to the I/O device.
Inventors
- 👤 Curtis Priem
- 👤 Rick Iwamoto
- 👤 Stephen Johnson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:01
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
190 words
A direct memory access (DMA) circuit for use with an input/output device and a system memory, the DMA circuit storing a first reference value pointing to a data structure which describes a buffer portion of the system memory in which data is stored for transfer to the input/output device, a first value, and a second value, wherein the first value determines a position within the buffer portion of the system memory beginning at which a next sequence of data is to be placed, and the second value determines a position within the buffer portion of the system memory beginning at which a next sequence of data is to be copied to the input/output device, wherein the DMA circuit includes: data transfer circuit configured to read data from the buffer portion of the system memory beginning at the position from which the next sequence of data is to be copied and to write the data read to the input/output device; and A state machine configured to respond to a jump instruction read by the data transfer circuit from the buffer portion by causing the DMA circuit to reset the second value.
Claim 2
Dependent Claim
190 words
A direct memory access (DMA) circuit for use with an input/output device and a system memory, the DMA circuit storing a first reference value pointing to a data structure which describes a buffer portion of the system memory in which data is stored for transfer to the input/output device, a first value, and a second value, wherein the first value determines a position within the buffer portion of the system memory beginning at which a next sequence of data is to be placed, and the second value determines a position within the buffer portion of the system memory beginning at which a next sequence of data is to be copied to the input/output device, wherein the DMA circuit includes: data transfer circuit configured to read data from the buffer portion of the system memory beginning at the position from which the next sequence of data is to be copied and to write the data read to the input/output device; and A state machine configured to respond to a jump instruction read by the data transfer circuit from the buffer portion by causing the DMA circuit to reset the second value.
Claim 3
Dependent Claim
73 words
The DMA circuit of claim 1, wherein the buffer portion of the system memory comprises memory locations identified by an initial position having an initial address and a final position having an address determined by the first address and an offset value, and wherein the state machine is configured to respond to the jump instruction by causing the DMA circuit to reset the second value to a value indicative of said initial position.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-18 | 2004-01-17 | 2004-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-18 | 2008-01-17 | 2008-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-18 | 2012-01-17 | 2012-07-18 | $7700.00 | Window Closed / Lapsed |