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US5828903A Expired / Lapsed US ⏱️ 0.0 years remaining

System for performing DMA transfer with a pipeline control switching such that the first storage area contains location of a buffer for subsequent transfer

Assignee: Intel Corp
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Filing: 1996-11-19
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Granted: 1998-10-27
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Expires: 2016-11-19
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Abstract

Abstract The present invention teaches a new system for transferring data between a network and hosts coupled to the network. The system uses an adapter, that is coupled between the host and the network, to allow segmenting and reassembling cells directly in the host memory. The present invention also teaches a pipelined DMA architecture to overcome the problem of the interruption of the DMA operation when switching from one virtual circuit to the next. This architecture depends on fast access to a local memory used for storing buffer descriptors for each virtual circuit. In this architecture, a two stage pipeline is used with the first stage performing the local memory access while the second stage performs the DMA transfers. When the pipeline is filled, both stages will operate in parallel yielding significant gain in performance due to continuous operation of the DMA.

Inventors

  • 👤 Jay Sethuram
  • 👤 Haim Sadger
  • 👤 Kevin C. Kahn
  • 👤 Farhad Mighani

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 20:52
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L2012/5638; H04L2012/5646; H04L2012/5652; H04L2012/5678; H04L2012/5681

Claims Analysis

Total Claims: 56
Claim 1
Independent Claim 119 words
A system for transferring information on a network comprising: a host device coupled to a network; a first and second storage area; and a pipeline control having a first pipeline stage for retrieving a location of a buffer for a next transfer and storing the location of the buffer for the next transfer in the second storage area and a second pipeline stage for performing a DMA transfer using a buffer for a current transfer, the location of the buffer for the current transfer stored in the first storage area, said pipeline control switching the first and second storage areas such that host devices stores an identification of a buffer for a subsequent transfer in the first storage area.
Claim 2
Independent Claim 119 words
A system for transferring information on a network comprising: a host device coupled to a network; a first and second storage area; and a pipeline control having a first pipeline stage for retrieving a location of a buffer for a next transfer and storing the location of the buffer for the next transfer in the second storage area and a second pipeline stage for performing a DMA transfer using a buffer for a current transfer, the location of the buffer for the current transfer stored in the first storage area, said pipeline control switching the first and second storage areas such that host devices stores an identification of a buffer for a subsequent transfer in the first storage area.
Claim 3
Dependent Claim 14 words
The system of claim 1, wherein the network is an asynchronous transfer mode network.
Claim 4
Dependent Claim 16 words
The system of claim 1, wherein data is transferred from the host device to the network.
Claim 5
Dependent Claim 16 words
The system of claim 1, wherein data is transferred from the network to the host device.
Claim 6
Dependent Claim 52 words
The system as set forth in claim 1, wherein the host device further includes an adapter coupled to the network, the adapter including the first and second storage area and the pipeline control the first and second storage areas including a register that stores the location of a buffer for a transfer.
Claim 7
Dependent Claim 29 words
The system as set forth in claim 1, wherein the host device includes a host memory, and further wherein the host memory includes the first and second storage area.
Claim 8
Dependent Claim 43 words
The system of claim 5, wherein a virtual circuit identifies the host, and the register is assigned to the virtual circuit such that when information is transferred on the virtual circuit, the assigned register identifies the location of the buffer for the transfer.
Claim 9
Dependent Claim 34 words
The system as set forth in claim 7, wherein the adapter further comprises a register pointer table, said table comprising a virtual circuit identification for the virtual circuit and a pointer to the register.
Claim 10
Dependent Claim 31 words
The system as set forth in claim 8, wherein the first pipeline stage and second pipeline stage repeatedly switch between the first and second storage areas to perform additional information transfers.
Claim 11
Dependent Claim 57 words
The system as set forth in claim 9, wherein said adapter further comprises a virtual circuit flag, said flag set when a transfer to be performed is to be performed on a different virtual circuit than an immediate prior transfer, said pipeline control switching the first and second storage areas when the virtual circuit flag is set.
Claim 12
Dependent Claim 45 words
The system as claimed in claim 5, wherein said adapter further comprises a mailbox for the temporary storage of communications between the host device and the adapter regarding status information of the transfer of information, said host device and said adapter accessing the status information.
Claim 13
Dependent Claim 17 words
The system as set forth in claim 11, wherein the mailbox is stored in adapter local memory.
Claim 14
Dependent Claim 31 words
The system as set forth in claim 11, wherein said adapter further comprises a mailbox flag, which when set, notifies the host device that status information is located in the mailbox.
Claim 15
Dependent Claim 30 words
The system as set forth in claim 11, wherein said adapter sets an interrupt in the host to notify the host device that status information is located in the mailbox.
Claim 16
Independent Claim 260 words
A method for a first device to receive information from a second device across a network via a path defined by one of at least one virtual circuit, said first device comprising a host memory and buffers located in said host memory, said first device coupled to an adapter comprising an adapter local memory and a direct memory access (DMA) engine, said method comprising the steps of: storing addresses of the buffers in at least one register, each register corresponding to one of said at least one virtual circuit; identifying a first register corresponding to a first virtual circuit path over which the information is received; transferring the address stored in said first register to a first storage area of the DMA engine of the adapter; initiating a DMA transfer wherein the received information is written to the buffer identified by the address stored in said first register; identifying a second register corresponding to a second virtual circuit path over which information is received and transferring the address stored in the second register to a second storage area of the DMA engine while the DMA engine performs a transfer to the buffer identified by the address stored in said first register; and performing a subsequent DMA transfer wherein the information received over the second virtual circuit is written to the buffer identified by the address stored in the second register while a resister corresponding to a virtual circuit other than the second virtual circuit is identified and the address stored in the register is transferred to the first storage area.
Claim 17
Independent Claim 260 words
A method for a first device to receive information from a second device across a network via a path defined by one of at least one virtual circuit, said first device comprising a host memory and buffers located in said host memory, said first device coupled to an adapter comprising an adapter local memory and a direct memory access (DMA) engine, said method comprising the steps of: storing addresses of the buffers in at least one register, each register corresponding to one of said at least one virtual circuit; identifying a first register corresponding to a first virtual circuit path over which the information is received; transferring the address stored in said first register to a first storage area of the DMA engine of the adapter; initiating a DMA transfer wherein the received information is written to the buffer identified by the address stored in said first register; identifying a second register corresponding to a second virtual circuit path over which information is received and transferring the address stored in the second register to a second storage area of the DMA engine while the DMA engine performs a transfer to the buffer identified by the address stored in said first register; and performing a subsequent DMA transfer wherein the information received over the second virtual circuit is written to the buffer identified by the address stored in the second register while a resister corresponding to a virtual circuit other than the second virtual circuit is identified and the address stored in the register is transferred to the first storage area.
Claim 18
Dependent Claim 38 words
The method as set forth in claim 15, wherein said step of storing addresses of the buffers comprises the step of storing the addresses of the buffers in at least one register located in the adapter local memory.
Claim 19
Dependent Claim 37 words
The method as set forth in claim 15, wherein said step of storing addresses of the buffers comprises the step of storing the addresses of the buffers in at least one register located in the host memory.
Claim 20
Dependent Claim 88 words
The method as set forth in claim 16, wherein said step of storing addresses of the buffers further comprises the step of generating a register pointer table in the adapter local memory, said table comprising a virtual circuit identification for each virtual circuit and a pointer to a corresponding register; and further wherein said step of transferring the address comprising the steps of referencing the register pointer table using the circuit identification to access the register pointer, and referencing the corresponding register pointed to by the register pointer.
Claim 21
Dependent Claim 63 words
The method as set forth in claim 18, wherein each of said registers further comprises status information and the step of copying the buffer address further comprises copying the contents of the register into the first storage area in the DMA engine; said method further comprising the step of writing the virtual circuit identification in the first storage area in the DMA engine.
Claim 22
Dependent Claim 56 words
The method as set forth in claim 19, further comprising the step of writing the contents of the first storage area in the DMA engine back to the register identified by the virtual circuit identification stored in the register in the DMA engine when the DMA engine completes the DMA transfer of information to the buffer.
Claim 23
Dependent Claim 82 words
The method as set forth in claim 19, wherein when new information is to be received via a different virtual circuit, said method further comprising the steps of: writing the contents of the first storage area in the DMA engine back to the register identified by the virtual circuit identification stored in the register in the DMA engine; and performing the steps of identifying a buffer address, transferring the identified buffer address and initiating a DMA transfer to receive the new information.
Claim 24
Dependent Claim 24 words
The method as set forth in claim 16, further comprising the step of notifying the first device of status of the receipt of data.
Claim 25
Dependent Claim 57 words
The method as set forth in claim 22, wherein the step of notifying comprises the steps of writing status information into adapter memory, setting a flag to indicate that status information is awaiting to be read by the first device, said first device polling the flag to determine when to read the adapter memory for status information.
Claim 26
Dependent Claim 42 words
The method as set forth in claim 22, wherein the step of notifying comprises the steps of writing status information into adapter memory, and setting an interrupt in the host to notify the host device that status information is to be read.
Claim 27
Dependent Claim 93 words
The method as set forth in claim 15, wherein information is transferred across the network in packed data units (PDUs) comprising a PDU header and PDU data, the step of initiating a DMA transfer comprises the step of each register identifying a header buffer of a size corresponding to the size of a PDU header, and a data buffer, said step of initiating a DMA transfer comprising the steps of: transferring the PDU header into a header buffer; and when the header buffer is full, transferring the PDU data into the data buffer.
Claim 28
Independent Claim 225 words
A method for transmitting data from a first device across a network to a second device, said first device comprising a host memory comprising at least one buffer, said method comprising the steps of: coupling an adapter between the first device and the network, said adapter comprising an adapter memory and a direct memory access (DMA) engine; said host writing the data to be transmitted into at least one buffer; said host generating an identification of a first buffer containing data for a first transfer; transferring the identification of the first buffer into a first storage area in the DMA engine; said adapter performing a DMA access to retrieve data from the identified first buffer and transmit the data contained in the first buffer across the network; said host generating an identification of a second buffer containing data for a second transfer and storing the identification of the second buffer in a second storage area in the DMA engine while the data contained in the first buffer is transmitted across the network; and switching the first and second storage areas such that the DMA engine transfers the data contained in the buffer identified in the second storage area while the host generates an identification of a buffer containing data for a subsequent transfer and stores the identification of the buffer in the first storage area.
Claim 29
Independent Claim 225 words
A method for transmitting data from a first device across a network to a second device, said first device comprising a host memory comprising at least one buffer, said method comprising the steps of: coupling an adapter between the first device and the network, said adapter comprising an adapter memory and a direct memory access (DMA) engine; said host writing the data to be transmitted into at least one buffer; said host generating an identification of a first buffer containing data for a first transfer; transferring the identification of the first buffer into a first storage area in the DMA engine; said adapter performing a DMA access to retrieve data from the identified first buffer and transmit the data contained in the first buffer across the network; said host generating an identification of a second buffer containing data for a second transfer and storing the identification of the second buffer in a second storage area in the DMA engine while the data contained in the first buffer is transmitted across the network; and switching the first and second storage areas such that the DMA engine transfers the data contained in the buffer identified in the second storage area while the host generates an identification of a buffer containing data for a subsequent transfer and stores the identification of the buffer in the first storage area.
Claim 30
Dependent Claim 57 words
The method as set forth in claim 26, said step of performing a DMA access further comprising the steps of retrieving a portion of data from the buffer during each access and transmitting the portion across the network, said step of retrieving a portion and transmitting the portion repeated until the contents of the buffer is transmitted.
Claim 31
Dependent Claim 27 words
The method as set forth in claim 26, further comprising the step of writing the identification of the first and second buffers into the adapter local memory.
Claim 32
Dependent Claim 26 words
The method as set forth in claim 26, further comprising the step of writing the identification of the first and second buffers into the host memory.
Claim 33
Dependent Claim 157 words
The method as set forth in claim 28, wherein data is transferred across the network via a path defined by one of at least one virtual circuit; said step of writing an identification of the first and second buffers into the adapter local memory comprising the step of generating virtual registers, each of said virtual registers comprising a buffer address; said method further comprising the step of generating a virtual register pointer table in the adapter local memory, said table comprising a virtual circuit identification for each virtual circuit and a pointer to a corresponding virtual register; said step of transferring comprising the steps of: referencing the virtual register pointer table using the virtual circuit identification to access the virtual register pointer; referencing the corresponding virtual register pointed to by the virtual register pointer; and copying the buffer address from the virtual register to the first storage area comprising at least one register in the DMA engine.
Claim 34
Dependent Claim 65 words
The method as set forth in claim 30, wherein each of the virtual registers further comprises status information and the step of copying the buffer address further comprises copying the contents of the virtual register into the first storage area in the DMA engine; said method further comprising the step of writing the virtual circuit identification in the first storage area in the DMA engine.
Claim 35
Dependent Claim 54 words
The method as set forth in claim 31, further comprising the step of writing the contents of the first storage area in the DMA engine back to the virtual register identified by the virtual circuit identification stored in the DMA engine when the DMA engine completes the DMA transfer of data from the buffer.
Claim 36
Dependent Claim 71 words
The method as set forth in claim 30, wherein the host writes data to be transferred across a virtual circuit in a plurality of buffers, said step of generating virtual registers further comprises generating a link pointer to point to a next virtual register of a plurality of virtual registers, each of the plurality of virtual registers comprising a buffer address of a buffer containing data written to by the host.
Claim 37
Dependent Claim 94 words
The method as set forth in claim 31, wherein when additional data has been written into buffers for transfer across a different virtual circuit, said method further comprising the steps of: writing the contents of the first storage area in the DMA engine back to the virtual register identified by the virtual circuit identification stored in the first storage area in the DMA engine; performing the steps of writing an identification of the buffer, transferring the identified buffer address and performing a DMA access to transfer the additional data across the different virtual circuit.
Claim 38
Dependent Claim 28 words
The method as set forth in claim 26, further comprising the step of notifying the first device of the status of the transfer of data across the network.
Claim 39
Dependent Claim 59 words
The method as set forth in claim 35, wherein the step of notifying comprises the steps of writing status information into adapter memory, setting a flag to indicate that status information is awaiting to be read by the first device, said first device polling the flag to determine when the adapter memory is to be read for status information.
Claim 40
Dependent Claim 42 words
The method as set forth in claim 35, wherein the step of notifying comprises the steps of writing status information into adapter memory, and setting an interrupt in the host to notify the host device that status information is to be read.
Claim 41
Dependent Claim 222 words
In a computer network comprising a plurality of devices coupled via a network, a device comprising a memory comprising at least one buffer for storing data transferred across the network, an adapter coupled between a device and the network for increasing the efficiency of transfers of data across the network comprising: at least one virtual register which identifies the location of the buffer in the device memory; a direct memorv access (DMA) engine comprising a first physical register block and a second physical register block, said device causing the information contained in the virtual register that identifies the location of the buffer for a current transfer to be copied into the second physical register block; a first pipeline stage for copying the information contained in the virtual register identified for a next transfer into the first physical register block; a second pipeline stage for performing a DMA transfer for the current transfer between the network and a buffer identified in the second physical register block; and a pipeline control for switching the first pipeline stage to copy information contained in the virtual register for a subsequent next transfer into the second physical register block, and switching the second pipeline stage to perform a DMA transfer for the next transfer between the network and a buffer identified in the first physical register block.
Claim 42
Dependent Claim 222 words
In a computer network comprising a plurality of devices coupled via a network, a device comprising a memory comprising at least one buffer for storing data transferred across the network, an adapter coupled between a device and the network for increasing the efficiency of transfers of data across the network comprising: at least one virtual register which identifies the location of the buffer in the device memory; a direct memorv access (DMA) engine comprising a first physical register block and a second physical register block, said device causing the information contained in the virtual register that identifies the location of the buffer for a current transfer to be copied into the second physical register block; a first pipeline stage for copying the information contained in the virtual register identified for a next transfer into the first physical register block; a second pipeline stage for performing a DMA transfer for the current transfer between the network and a buffer identified in the second physical register block; and a pipeline control for switching the first pipeline stage to copy information contained in the virtual register for a subsequent next transfer into the second physical register block, and switching the second pipeline stage to perform a DMA transfer for the next transfer between the network and a buffer identified in the first physical register block.
Claim 43
Dependent Claim 25 words
The adapter as set forth in claim 38, further comprising an adapter local memory, wherein the virtual register is stored in the adapter local memory.
Claim 44
Dependent Claim 55 words
The adapter as set forth in claim 38, wherein a virtual circuit identifies the transmitting device and receiving device of data, and the virtual register is assigned to a virtual circuit such that when data is transmitted on the virtual circuit, the assigned virtual register identifies the location of the buffer data is transferred to.
Claim 45
Dependent Claim 34 words
The adapter as set forth in claim 38, further comprising a virtual register pointer table, said table comprising a virtual circuit identification for each virtual circuit and a pointer to a corresponding virtual register.
Claim 46
Dependent Claim 23 words
The adapter as set forth in claim 41, wherein the first stage and second stage are repeatedly switched to perform additional data transfers.
Claim 47
Dependent Claim 41 words
The adapter as set forth in claim 38, further comprising a mailbox for the temporary storage of communications between the device and the adapter regarding status information of the transfer of data, said device and said adapter accessing the status information.
Claim 48
Dependent Claim 212 words
In a computer network comprising a plurality of devices coupled via a network, a device comprising a memory comprising at least one buffer for storing data transferred across the network, an adapter coupled between a device and the network for increasing the efficiency of transfers of data across the network, comprising: means for identifying the location of a first and a second buffer in the device memory; processing means for performing a current transfer of data directly between the first buffer in the device memory and the network; first and second register means for storing the location of the first and second buffers in the device memory; and means for copying the location of the second buffer to the second register means when a subsequent transfer of data is to be performed between the second buffer and the network, said copying performed while the processing means performs the current transfer, said processing means accessing the second register means to perform the subsequent transfer of data, said means for copying further including means for switching the first and second register means such that a subsequent data transfer uses the buffer identified by the second register means while the identification of a buffer for a subsequent transfer is stored in the first register means.
Claim 49
Dependent Claim 212 words
In a computer network comprising a plurality of devices coupled via a network, a device comprising a memory comprising at least one buffer for storing data transferred across the network, an adapter coupled between a device and the network for increasing the efficiency of transfers of data across the network, comprising: means for identifying the location of a first and a second buffer in the device memory; processing means for performing a current transfer of data directly between the first buffer in the device memory and the network; first and second register means for storing the location of the first and second buffers in the device memory; and means for copying the location of the second buffer to the second register means when a subsequent transfer of data is to be performed between the second buffer and the network, said copying performed while the processing means performs the current transfer, said processing means accessing the second register means to perform the subsequent transfer of data, said means for copying further including means for switching the first and second register means such that a subsequent data transfer uses the buffer identified by the second register means while the identification of a buffer for a subsequent transfer is stored in the first register means.
Claim 50
Dependent Claim 229 words
In a computer network comprising a plurality of devices coupled via a network, wherein data is transferred over virtual circuits on the network, a device comprising a memory comprising at least one buffer for storing data transferred across the network, an adapter coupled between a device and the network for increasing the efficiency of transfers of data across the network comprising: a virtual register for storing an address of the at least one buffer, each buffer and virtual register corresponding to a virtual circuit; a first physical register; a second physical register; a first pipeline stage, said first pipeline stage copying the address of the buffer to the first physical register for a next virtual circuit over which data is to be transferred; a second pipeline stage for performing a current transfer of data over a current virtual circuit, said second pipeline stage referencing a buffer address stored in the second physical register directly transferring data between the network and the buffer; and a control switch for switching the first physical register and the second physical register such that the first pipeline stage copies the address of the buffer to the second physical register for a subsequent next virtual circuit, and the second pipeline stage performs a transfer of data over the next virtual circuit, said second pipeline stage referencing a buffer address stored in the first physical register.
Claim 51
Dependent Claim 229 words
In a computer network comprising a plurality of devices coupled via a network, wherein data is transferred over virtual circuits on the network, a device comprising a memory comprising at least one buffer for storing data transferred across the network, an adapter coupled between a device and the network for increasing the efficiency of transfers of data across the network comprising: a virtual register for storing an address of the at least one buffer, each buffer and virtual register corresponding to a virtual circuit; a first physical register; a second physical register; a first pipeline stage, said first pipeline stage copying the address of the buffer to the first physical register for a next virtual circuit over which data is to be transferred; a second pipeline stage for performing a current transfer of data over a current virtual circuit, said second pipeline stage referencing a buffer address stored in the second physical register directly transferring data between the network and the buffer; and a control switch for switching the first physical register and the second physical register such that the first pipeline stage copies the address of the buffer to the second physical register for a subsequent next virtual circuit, and the second pipeline stage performs a transfer of data over the next virtual circuit, said second pipeline stage referencing a buffer address stored in the first physical register.
Claim 52
Dependent Claim 54 words
The adapter as set forth in claim 45, further comprising a virtual circuit flag, said flag set when a transfer to be performed is to be performed on a different virtual circuit than an immediate prior transfer, said pipeline control switching the first and second physical registers when the virtual circuit flag is set.
Claim 53
Dependent Claim 221 words
In a computer network comprising a plurality of devices coupled via a network, wherein data is transferred over virtual circuits on the network, a device comprising a memory comprising at least one buffer for storing data transferred across the network, said transfer of data performed by an adapter coupled between the device and the network, a method for transferring data comprising the steps of: storing an address of the at least one buffer, each buffer corresponding to a virtual circuit; providing a first physical register and a second physical register; a first pipeline stage of the adapter copying the address of the buffer to the first physical register for a next virtual circuit over which data is to be transferred; a second pipeline stage performing a current transfer of data over a current virtual circuit, said second pipeline stage referencing a buffer address stored in the second physical register directly transferring data between the network and the buffer; and switching the first physical register and the second physical register such that the first pipeline stage copies the address of the buffer to the second physical register for a subsequent next virtual circuit, and the second pipeline stage performs a transfer of data over the next virtual circuit, said second pipeline stage referencing a buffer address stored in the first physical register.
Claim 54
Dependent Claim 221 words
In a computer network comprising a plurality of devices coupled via a network, wherein data is transferred over virtual circuits on the network, a device comprising a memory comprising at least one buffer for storing data transferred across the network, said transfer of data performed by an adapter coupled between the device and the network, a method for transferring data comprising the steps of: storing an address of the at least one buffer, each buffer corresponding to a virtual circuit; providing a first physical register and a second physical register; a first pipeline stage of the adapter copying the address of the buffer to the first physical register for a next virtual circuit over which data is to be transferred; a second pipeline stage performing a current transfer of data over a current virtual circuit, said second pipeline stage referencing a buffer address stored in the second physical register directly transferring data between the network and the buffer; and switching the first physical register and the second physical register such that the first pipeline stage copies the address of the buffer to the second physical register for a subsequent next virtual circuit, and the second pipeline stage performs a transfer of data over the next virtual circuit, said second pipeline stage referencing a buffer address stored in the first physical register.
Claim 55
Dependent Claim 56 words
The method as set forth in claim 47, further comprising the step of setting a flag when the step of switching is to be performed, said step of setting performed when a transfer is to be performed on a different virtual circuit than the virtual circuit over which transfers are performed by the second pipeline stage.
Claim 56
Dependent Claim 41 words
The method as set forth in claim 47; wherein the step of switching is performed when a transfer is to be performed on a different virtual circuit than the virtual circuit over which transfers are performed by the second pipeline stage.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2001-10-26 2002-04-27 2002-10-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2005-10-26 2006-04-27 2006-10-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2009-10-26 2010-04-27 2010-10-27 $7700.00 Window Closed / Lapsed

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