Apparatus for the microprogram control of information transfer and a method for operating the same

Claim 2

Circuit arrangement in a direct memory access controller having a plurality of independent data transmission channels for autonomous data transmission between a plurality of data sources and data sinks, the circuit arrangement comprising a microprogram, a microprogram memory for storing said microprogram, a plurality of microprogram instruction registers, one for each of said data transmission channels, having inputs connected to said microprogram memory, each microprogram instruction register operating to store a respective channel-specific microprogram instruction, and each microprogram instruction register receiving said respective microprogram instruction from said microprogram memory, a microprogram interim memory having an input connected to said microprogram instruction registers for receiving a respective microprogram instruction from one of said microprogram instruction registers for a current data transmission, controlling means having inputs connected to said microprogram interim memory for controlling said current data transmission, said controlling means being connected to said microprogram interim memory and being responsive to said respective microprogram instruction for execution of said microprogram instruction, an independently operating data handling unit for determining presence of an access byte/word during data transmission having an input connected to said controlling means, a data assembly register having an input connected to said data handling unit, and respective outputs assigned to each of said data transmission channels for temporary storage of data bits or control information, means in said data handling unit for, after microprogrammed initialization, executing channel-specific processing of the data transmission.

Claim 3

Circuit arrangement according to claim 1, wherein said data handling unit further comprises an off-set controller and an execution controller, connected to said data assembly register, for exchanging information with said data sinks and said data sources.

Claim 4

Circuit arrangement according to claim 1, including at least one control flip-flop connected to said data handling unit for controlling entry and exit sequence of data in said data handling unit.

Claim 5

Circuit arrangement according to claim 1, wherein said handling unit further comprises a match-verify unit for executing data comparisons.

Claim 6

Method for operating a circuit arrangement in a direct memory access controller having a plurality of independent data transmission channels for autonomous data transmission between a plurality of data sources and data sinks, a microprogram, comprising channel-specific microprogram instructions, stored in a microprogram memory, a plurality of microprogram instruction registers, one for each of said data transmission channels, having inputs connected to said microprogram memory, each of said microprogram instruction registers storing a respective channel-specific microprogram instruction, a microprogram interim memory having an input connected to said microprogram instruction registers, controlling means for controlling transmission of data having inputs connected to said microprogram interim memory and being responsive to said channel-specific microprogram instructions, an independently operating data handling unit having an input connected to said controlling means, a data assembly register having an input connected to said data handling unit and respective outputs assigned to each of said data transmission channels for temporary storage of data bits on control information, means in said data handling unit for, after microprogrammed initialization, executing channel-specific processing of the data transmission, the method comprises the steps of: (a) executing, by said controlling means, a channel-specific microprogram instruction from one of said plurality of microprogram instruction registers; said data handling unit receiving said channel-specific microprogram instruction from said controlling means; (b) executing, after microprogram initialization of said data handling unit, channel-specific transmission of data in a respective data transmission channel; and (c) determining, independently by said data handling unit, presence of an access byte-word during an information transfer to one of said data transmission channels.

Claim 7

Method for operating a circuit arrangement in a direct memory access controller having a plurality of independent data transmission channels for autonomous data transmission between a plurality of data sources and data sinks, a microprogram, comprising channel-specific microprogram instructions, stored in a microprogram memory, a plurality of microprogram instruction registers, one for each of said data transmission channels, having inputs connected to said microprogram memory, each of said microprogram instruction registers storing a respective channel-specific microprogram instruction, a microprogram interim memory having an input connected to said microprogram instruction registers, controlling means for controlling transmission of data having inputs connected to said microprogram interim memory and being responsive to said channel-specific microprogram instructions, an independently operating data handling unit having an input connected to said controlling means, a data assembly register having an input connected to said data handling unit and respective outputs assigned to each of said data transmission channels for temporary storage of data bits on control information, means in said data handling unit for, after microprogrammed initialization, executing channel-specific processing of the data transmission, the method comprises the steps of: (a) executing, by said controlling means, a channel-specific microprogram instruction from one of said plurality of microprogram instruction registers; said data handling unit receiving said channel-specific microprogram instruction from said controlling means; (b) executing, after microprogram initialization of said data handling unit, channel-specific transmission of data in a respective data transmission channel; and (c) determining, independently by said data handling unit, presence of an access byte-word during an information transfer to one of said data transmission channels.

Claim 8

Method according to claim 5, wherein said data assembly register has two halves, further comprising the step of activating the data assembly register halves with the data handling unit for transfer of data.

Claim 9

Method according to claim 6, including a bus interface unit connected to said data transmission channels and a swapper in the bus interface unit, and internal data buses connected to the data assembly register and the bus interface unit, further comprising the step of controlling said internal data buses with said data handling unit.

Claim 10

Method according to claim 6, further comprising the step of controlling with said data handling unit, operations for comparing, mismatching, and/or verifying data.

Claim 11

Method according to claim 6, including control parameters DARFST, FIRST, DARBYTE, and DARPE in said data assembly register, further comprising the step of managing said control parameters with said data handling unit.

Claim 12

Method according to claim 6, including an offset value in said data handling unit, an address pointer registers for storing an address pointer, and an adder connected to said address pointer and said register and said, further comprising the step of adding said offset value to said address pointer via said adder each direct memory access operation.