US4344130A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus to execute DMA transfer between computing devices using a block move instruction
Assignee: Unisys Corp
•
Filing: 1979-09-26
•
Granted: 1982-08-10
•
Expires: 1999-09-26
Abstract
Abstract There is shown and described a method and apparatus for using a "block move" instruction in a microprocessor to execute the direct memory access (DMA) data transfer function between a microprocessor and a minicomputer. The instruction permits an apparent data transfer in the memory of the microprocessor to be utilized to transfer data to the memory in the minicomputer. Little or no additional hardware over existing systems is required.
Inventors
- 👤 Anthony K. Fung
- 👤 Roger G. Mintzlaff
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 02:22
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/167
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
253 words
In combination, first computing means having memory means associated therewith, said first computing means including a "block move instruction" capability, second computing means having memory means associated therewith, first register means for selectively transferring data from said first computing means to said second computing means, second register means for selectively transferring data from said second computing means to said first computing means, first bus means connected to said first computing means and each of said first and second register means for transferring data, second bus means connected to said second computing means and each of said first and second register means for transferring data, and control means for controlling the operation of said first and second register means and said first and second computing means, said control means includes means responsive to signals from said first computing means to provide an indication signal to indicate that said "block move instruction" is being performed by said first computing means, said control means further includes means responsive to signals from said second computing means and to said indication signal to indicate to said control means that said second computing means desires to transfer information to or from said first computing means when said "block move instruction" is being performed by said first computing means, whereby data in said first computing means is transferred directly to said second computing means, or vice versa, depending upon which of said first and second register means is enabled for transferring data without the requirement of request and acknowledge signals.
Claim 2
Dependent Claim
253 words
In combination, first computing means having memory means associated therewith, said first computing means including a "block move instruction" capability, second computing means having memory means associated therewith, first register means for selectively transferring data from said first computing means to said second computing means, second register means for selectively transferring data from said second computing means to said first computing means, first bus means connected to said first computing means and each of said first and second register means for transferring data, second bus means connected to said second computing means and each of said first and second register means for transferring data, and control means for controlling the operation of said first and second register means and said first and second computing means, said control means includes means responsive to signals from said first computing means to provide an indication signal to indicate that said "block move instruction" is being performed by said first computing means, said control means further includes means responsive to signals from said second computing means and to said indication signal to indicate to said control means that said second computing means desires to transfer information to or from said first computing means when said "block move instruction" is being performed by said first computing means, whereby data in said first computing means is transferred directly to said second computing means, or vice versa, depending upon which of said first and second register means is enabled for transferring data without the requirement of request and acknowledge signals.
Claim 3
Dependent Claim
24 words
The combination recited in claim 1 wherein said control means includes stored memory means for providing specified control signals in response to input signals.
Claim 4
Dependent Claim
26 words
The combination recited in claim 1 wherein said first register means includes data register means and address register means for transferring data and address information, respectively.
Claim 5
Dependent Claim
23 words
The combination recited in claim 1 wherein said control means includes logic circuit means for selectively enabling said first and second register means.
Claim 6
Dependent Claim
23 words
The combination recited in claim 1 wherein said first computing means comprises a microprocessor, and said second computing means comprises a minicomputer system.
Claim 7
Dependent Claim
34 words
The combination recited in claim 2 wherein said stored memory means comprises a read-only memory which selectively produces output control signals as a function of input control signals which are supplied as address signals.
Claim 8
Dependent Claim
37 words
The combination recited in claim 6 wherein said output control signals are supplied to each of said first and second register means to selectively enable only one of said first and second register means at a time.
Claim 9
Dependent Claim
36 words
The combination recited in claim 3 wherein said data register means includes upper and lower data byte registers to operate on selected byte portions of a data word to be transferred to said second computing means.
Claim 10
Dependent Claim
38 words
The combination recited in claim 3 wherein said address register means shifts the address information supplied from said first computing means by at least one bit in order to increase the data packing in said second computing means.
Claim 11
Dependent Claim
39 words
The combination recited in claim 9 wherein, said first and second computing means have different word length operating characteristics and said address register means shifts the address information sufficiently to permit interaction of said first and second computing means.
Claim 12
Dependent Claim
28 words
The combination recited in claim 10 wherein, said first computing means has a word length of 8-bit and said second computing means has a word length of 16-bits.
Claim 13
Dependent Claim
21 words
The combination recited in claim 1 including memory map register means for mapping the memory means in said second computing means.
Claim 14
Dependent Claim
30 words
The combination recited in claim 1 wherein, said block move instruction permits a large amount of information to be moved from one location in memory to another location in memory.
Claim 15
Dependent Claim
70 words
The combination recited in claim 13 wherein, said large amount of information is transferred directly from the memory means associated with said first computing means to the memory means associated with said second computing means, or vice versa, depending upon which of said first and second register means is enabled for transferring data without loss of integrity of said information or the remainder of the information stored in either memory.
Claim 16
Dependent Claim
26 words
The combination recited in claim 1 wherein, said control means includes latch means for producing a signal indicative of the performance of said block move instruction.
Claim 17
Dependent Claim
37 words
The combination recited in claim 1 wherein, said control means selectively produces a disable signal which disables the memory associated with said first computing means when information is to be transferred therefrom to said second computing means.
References Cited (Backward Citations)
US3932841A
Cited
US3940743A
Cited
US4035777A
Cited
US4130865A
Cited
US3969704A
Cited
US4050096A
Cited
US4086627A
Cited
US4124888A
Cited
US4112490A
Cited
US4099236A
Cited
US4128883A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-08-09 | 1986-02-08 | 1986-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-08-09 | 1990-02-08 | 1990-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-08-09 | 1994-02-08 | 1994-08-10 | $7700.00 | Window Closed / Lapsed |