US5333290A
Expired / Lapsed
US
⏱️ 0.0 years remaining
DMA controller having jump function
Assignee: NEC Electronics Corp
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Filing: 1991-08-08
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Granted: 1994-07-26
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Expires: 2011-08-08
Abstract
Abstract A direct memory access (DMA); controller for controlling data transfer between a memory and an input/output (I/O) device comprises an address counter for counting an address to be supplied to the memory, and a read/write controller for controlling a read/write operation between the memory and the I/O device. A jump start address register is provided to hold a jump start address, and an address comparator compares a content of the address counter with a content of the jump start address register. When the address comparator detects consistence between the content of the address counter and the content of the jump start address register, the read/write controller operates to stop the read/write operation between the memory and the I/O device.
Inventors
- 👤 Taiji Kato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:14
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
226 words
A direct memory access (DMA) controller for controlling data transfer between a memory and an input/output (I/O) device, the DMA controller comprising: an address counter for counting an address to be supplied to said memory, a read/write controller for controlling a read/write operation between said memory and said I/O device, a jump start address register for holding a jump start address, an address comparator for comparing a content of said address counter with a content of said jump start address register, said read/write controller operating to stop said read/write operation between said memory and said I/O device when said address comparator detects consistence between said content of said address counter and said content of said jump start address register, and means for updating said content of said address counter, wherein said address counter is updated by said means for updating while said read/write controller operates to stop said read/write operation, said DMA controller further including a jump end address register for holding a jump end address, said address comparator operating to compare said content of said address counter with a content of said jump end address register, and said read/write controller operating to restart said read/write operation between said memory and said I/O device when said address comparator detects consistence between said content of said address counter and said content of said jump end address register.
Claim 2
Dependent Claim
226 words
A direct memory access (DMA) controller for controlling data transfer between a memory and an input/output (I/O) device, the DMA controller comprising: an address counter for counting an address to be supplied to said memory, a read/write controller for controlling a read/write operation between said memory and said I/O device, a jump start address register for holding a jump start address, an address comparator for comparing a content of said address counter with a content of said jump start address register, said read/write controller operating to stop said read/write operation between said memory and said I/O device when said address comparator detects consistence between said content of said address counter and said content of said jump start address register, and means for updating said content of said address counter, wherein said address counter is updated by said means for updating while said read/write controller operates to stop said read/write operation, said DMA controller further including a jump end address register for holding a jump end address, said address comparator operating to compare said content of said address counter with a content of said jump end address register, and said read/write controller operating to restart said read/write operation between said memory and said I/O device when said address comparator detects consistence between said content of said address counter and said content of said jump end address register.
Claim 3
Dependent Claim
209 words
A direct memory access controller for controlling data transfer between a memory and an input/output device, the direct memory access controller comprising: an address counter for counting an address to be supplied to said memory; a read/write controller for controlling a read/write operation between said memory and said input/output device; a jump start address register for holding a jump start address; a jump end address register for holding a jump end address; means for updating a content of said address counter; and an address comparator for comparing said content of said address counter with a content of said jump start address register and a content of said jump end address register, said read/write controller operating to stop said read/write operation between said memory and said input/output device when said address comparator detects consistence between said content of said address counter and said content of said jump start address register, said address counter continuing to be updated by said means for updating while said read/write controller operates to stop said read/write operation, said read/write controller operating to restart said read/write operation between said memory and said input/output device when said address comparator detects consistence between said content of said address counter and said content of said jump end address register.
Claim 4
Dependent Claim
209 words
A direct memory access controller for controlling data transfer between a memory and an input/output device, the direct memory access controller comprising: an address counter for counting an address to be supplied to said memory; a read/write controller for controlling a read/write operation between said memory and said input/output device; a jump start address register for holding a jump start address; a jump end address register for holding a jump end address; means for updating a content of said address counter; and an address comparator for comparing said content of said address counter with a content of said jump start address register and a content of said jump end address register, said read/write controller operating to stop said read/write operation between said memory and said input/output device when said address comparator detects consistence between said content of said address counter and said content of said jump start address register, said address counter continuing to be updated by said means for updating while said read/write controller operates to stop said read/write operation, said read/write controller operating to restart said read/write operation between said memory and said input/output device when said address comparator detects consistence between said content of said address counter and said content of said jump end address register.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-25 | 1998-01-24 | 1998-07-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-25 | 2002-01-24 | 2002-07-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-25 | 2006-01-24 | 2006-07-26 | $7700.00 | Window Closed / Lapsed |