US5933654A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic buffer fracturing by a DMA controller
Assignee: Allen Bradley Co LLC
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Filing: 1996-09-24
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Granted: 1999-08-03
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Expires: 2016-09-24
Abstract
Abstract A data control system having a host microprocessor, a data receiving device and a DMA controller. The DMA controller being used to control the fragmentation and recombination of a buffer memory area. The data being processed in data packets and using DMA buffer chaining.
Inventors
- 👤 Daniel J. Galdun
- 👤 Peter J. Boldt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:15
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
114 words
A control system comprising: a receiving device configured to receive externally provided data; a host processor for processing the data; a system memory including a buffer memory area for storing the data wherein the data in said buffer memory area is non-fractured and stored in substantially contiguous memory locations; and a DMA controller in operational connection with the receiving device, the host processor, and the system memory, the DMA controller providing buffer management control for controlling the storage of the data in the buffer memory area wherein said buffer management control further comprises dynamically fracturing the buffer memory area, whereby the dynamic fracturing forms substantially contiguous smaller memory fragments from said buffer memory area.
Claim 2
Dependent Claim
114 words
A control system comprising: a receiving device configured to receive externally provided data; a host processor for processing the data; a system memory including a buffer memory area for storing the data wherein the data in said buffer memory area is non-fractured and stored in substantially contiguous memory locations; and a DMA controller in operational connection with the receiving device, the host processor, and the system memory, the DMA controller providing buffer management control for controlling the storage of the data in the buffer memory area wherein said buffer management control further comprises dynamically fracturing the buffer memory area, whereby the dynamic fracturing forms substantially contiguous smaller memory fragments from said buffer memory area.
Claim 3
Dependent Claim
28 words
The control system according to claim 1 wherein a plurality of buffer descriptors are provided in system memory, each corresponding to data stored in the buffer memory area.
Claim 4
Dependent Claim
16 words
The control system according to claim 2 wherein the plurality of buffer descriptors are chained together.
Claim 5
Dependent Claim
37 words
The control system according to claim 3 wherein each buffer descriptor includes a status and control word, a word containing a length of a data buffer area and a pointer to the start of a data buffer.
Claim 6
Dependent Claim
89 words
The control system according to claim 4 wherein the DMA controller adjusts the information in a plurality of buffer descriptors such that data stored in the data buffer area is stored in said substantially contiguous non-fractured memory locations, irrespective of a size of data being stored, and wherein said dynamic fracturing of the buffer memory area comprises dynamic fracturing or fragmentation of the buffer memory area into said smaller contiguous memory fragments and wherein the DMA controller dynamically recombines said smaller memory fragments during control system operation for reuse.
Claim 7
Dependent Claim
22 words
The control system according to claim 1 wherein the data is transferred within the control system in data packets of varying sizes.
Claim 8
Dependent Claim
17 words
The control system according to claim 1 wherein the receiving device is a media access interface chip.
Claim 9
Dependent Claim
44 words
The control system according to claim 7 wherein the DMA controller is interruptible by the media access interface chip, and is further configured with the media access interface chip to access internal registers of the media access interface chip to interrogate and acknowledge interrupts.
Claim 10
Dependent Claim
25 words
The control system according to claim 8 wherein the DMA controller is configured to support an implicit mode of transfer of the media access chip.
Claim 11
Dependent Claim
47 words
The control system according to claim 1 wherein the DMA, controller, having at least one data channel and internal registers, and host processor are configured together such that the host processor configures the at least one data channel by commands and data written to the internal registers.
Claim 12
Dependent Claim
39 words
The control system according to claim 1 wherein movement of the data from the receiving device to the system memory is in a unit of a MAC frame, the MAC frame being comprised of a plurality of data packets.
Claim 13
Independent Claim
203 words
A method of controlling storage of data in a buffer memory area of a control system including a host processor, a system memory, a DMA controller and a receiving device all in operational connection with each other and where the receiving device receives external data which is stored in the buffer memory area located in the system memory, the method comprising the steps of: determining, by the DMA controller, a first amount of data which is being stored in a first area of the buffer memory area; storing the first amount of data in the first area of the buffer memory area; fragmenting the first area of the buffer memory area such that the fragmented first area is substantially equal to the first amount of data stored therein, whereby additional data is prevented from being written to the fragmented area; repeating the determining, storing and fragmenting steps for additionally received data; and wherein the repeated determining, fragmenting, and storing steps further include determining the size of the data, fragmenting a portion of the buffer memory area to a corresponding size, and storing the data in the fragmented portion such that the fragmented portions of buffer memory area are substantially contiguous to each other.
Claim 14
Independent Claim
203 words
A method of controlling storage of data in a buffer memory area of a control system including a host processor, a system memory, a DMA controller and a receiving device all in operational connection with each other and where the receiving device receives external data which is stored in the buffer memory area located in the system memory, the method comprising the steps of: determining, by the DMA controller, a first amount of data which is being stored in a first area of the buffer memory area; storing the first amount of data in the first area of the buffer memory area; fragmenting the first area of the buffer memory area such that the fragmented first area is substantially equal to the first amount of data stored therein, whereby additional data is prevented from being written to the fragmented area; repeating the determining, storing and fragmenting steps for additionally received data; and wherein the repeated determining, fragmenting, and storing steps further include determining the size of the data, fragmenting a portion of the buffer memory area to a corresponding size, and storing the data in the fragmented portion such that the fragmented portions of buffer memory area are substantially contiguous to each other.
Claim 15
Dependent Claim
49 words
The method according to claim 12 further including a step by the DMA controller of recompiling, including, checking fragmented buffer memory areas to determine if the data located therein is required by the host processor; and combining fragmented buffer memory areas which are not required by the host processor.
Claim 16
Dependent Claim
23 words
The method according to claim 12 wherein the step of fragmenting includes changing information located within a buffer descriptor located in system memory.
Claim 17
Dependent Claim
26 words
The method according to claim 12 wherein the repeating step is repeated for all data descriptors located in system memory combined in a data descriptor chain.
Claim 18
Dependent Claim
144 words
A control system comprising: a receiving device configured to receive externally provided data; a host processor for processing the data; a system memory including a buffer memory area for storing the data wherein the data in said buffer memory area is non-fractured and stored in substantially contiguous memory locations; and a DMA controller in operational connection with the receiving data, the host processor, and the system memory, the DMA controller providing buffer management control for controlling the storage of the data in the buffer memory area, such that data stored in the buffer memory area are stored in contiguous non-fractured memory locations in the buffer memory area, irrespective of a size of data being stored, and wherein said buffer management control further comprises dynamically fracturing the buffer memory area, whereby the dynamic fracturing forms substantially contiguous smaller memory fragments from said buffer memory area.
Claim 19
Dependent Claim
144 words
A control system comprising: a receiving device configured to receive externally provided data; a host processor for processing the data; a system memory including a buffer memory area for storing the data wherein the data in said buffer memory area is non-fractured and stored in substantially contiguous memory locations; and a DMA controller in operational connection with the receiving data, the host processor, and the system memory, the DMA controller providing buffer management control for controlling the storage of the data in the buffer memory area, such that data stored in the buffer memory area are stored in contiguous non-fractured memory locations in the buffer memory area, irrespective of a size of data being stored, and wherein said buffer management control further comprises dynamically fracturing the buffer memory area, whereby the dynamic fracturing forms substantially contiguous smaller memory fragments from said buffer memory area.
Claim 20
Dependent Claim
28 words
The control system according to claim 16 wherein a plurality of buffer descriptors are provided in system memory, each corresponding to data stored in the buffer memory area.
Claim 21
Dependent Claim
16 words
The control system according to claim 17 wherein the plurality of buffer descriptors are chained together.
Claim 22
Dependent Claim
111 words
The control system according to claim 18 wherein each buffer descriptor includes a status and control word, a word containing a length of a data buffer area and a pointer to the start of a data buffer, wherein the DMA controller adjusts the information in a plurality of buffer descriptors to ensure that data stored in the data buffer area is stored in the substantially contiguous memory locations, and wherein said dynamic fracturing of the buffer memory area comprises dynamic fracturing or fragmentation of the buffer memory area into said smaller contiguous memory fragments and wherein the DMA controller dynamically recombines said smaller memory fragments during control system operation for reuse.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-08-02 | 2003-02-01 | 2003-08-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-08-02 | 2007-02-01 | 2007-08-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-08-02 | 2011-02-01 | 2011-08-03 | $7700.00 | Window Closed / Lapsed |