Methods of forming integrated circuitry and integrated circuitry structures

Claim 1

A method of forming integrated circuitry comprising: forming a plurality of layers over a substrate; etching a series of first trenches into a first of the layers and extending along a first direction generally parallel to a top surface of the substrate; etching a series of second trenches into the first layer and extending along a second direction which is different from the first direction, the second direction being generally parallel to the top surface of the substrate, the first and second trenches defining a plurality of different substrate elevations, adjacent elevations being joined by sidewalls which extend therebetween; forming sidewall spacers over the sidewalls; selectively etching material of the first layer relative to material from which the spacers are formed; and removing the material from which the spacers are formed.

Claim 2

A method of forming integrated circuitry comprising: forming a plurality of layers over a substrate; etching a series of first trenches into a first of the layers and extending along a first direction generally parallel to a top surface of the substrate; etching a series of second trenches into the first layer and extending along a second direction which is different from the first direction, the second direction being generally parallel to the top surface of the substrate, the first and second trenches defining a plurality of different substrate elevations, adjacent elevations being joined by sidewalls which extend therebetween; forming sidewall spacers over the sidewalls; selectively etching material of the first layer relative to material from which the spacers are formed; and removing the material from which the spacers are formed.

Claim 18

A method of forming integrated circuitry comprising: forming a layer of material over a substrate; etching a series of first trenches into the layer and extending along a first direction generally parallel to a top surface of the substrate; etching a series of second trenches into the layer and in a second direction which is different from the first direction, the second direction being generally parallel to the top surface of the substrate, the first and second trenches defining a plurality of different substrate elevations, adjacent elevations being joined by sidewalls which extend therebetween; forming sidewall spacers over the sidewalls; selectively etching material of the layer relative to material from which the spacers are formed, the etching defining a plurality of cells at least some adjacent cells being separated from one another by no more than a width dimension of a respective one of the spacers; and removing material comprising the spacer material.

Claim 19

A method of forming integrated circuitry comprising: forming a layer of material over a substrate; etching a series of first trenches into the layer and extending along a first direction generally parallel to a top surface of the substrate; etching a series of second trenches into the layer and in a second direction which is different from the first direction, the second direction being generally parallel to the top surface of the substrate, the first and second trenches defining a plurality of different substrate elevations, adjacent elevations being joined by sidewalls which extend therebetween; forming sidewall spacers over the sidewalls; selectively etching material of the layer relative to material from which the spacers are formed, the etching defining a plurality of cells at least some adjacent cells being separated from one another by no more than a width dimension of a respective one of the spacers; and removing material comprising the spacer material.

Claim 27

A method of forming integrated circuitry comprising: forming at least two layers over a substrate; forming sidewalls in a first of the layers and at different relative elevations; forming sidewall spacers over the sidewalls; first etching material of the layers substantially selective relative to the spacers; and second etching different material of the layers substantially selective relative to the material of the layers first etched.

Claim 28

A method of forming integrated circuitry comprising: forming at least two layers over a substrate; forming sidewalls in a first of the layers and at different relative elevations; forming sidewall spacers over the sidewalls; first etching material of the layers substantially selective relative to the spacers; and second etching different material of the layers substantially selective relative to the material of the layers first etched.

Claim 41

A method of forming integrated circuitry comprising: forming an array of sidewall spacers over a plurality of layers of material which are formed over a substrate, the spacers having respective lateral width dimensions; and etching at least some of the plurality of layers sufficiently to transfer the lateral width dimensions of the array of spacers into the plurality of layers, the etching defining a plurality of cells, at least some adjacent cells being separated from one another by no more than an individual spacer lateral width dimension.

Claim 42

A method of forming integrated circuitry comprising: forming an array of sidewall spacers over a plurality of layers of material which are formed over a substrate, the spacers having respective lateral width dimensions; and etching at least some of the plurality of layers sufficiently to transfer the lateral width dimensions of the array of spacers into the plurality of layers, the etching defining a plurality of cells, at least some adjacent cells being separated from one another by no more than an individual spacer lateral width dimension.

Claim 55

A method of forming integrated circuitry comprising: providing a substrate; forming an assembly of layers over the substrate; defining a matrix comprising a plurality of elevational planes disposed within said assembly, said planes defining three different elevations relative to the substrate, said three different elevations comprising a lowermost elevation, an intermediate elevation, and an uppermost elevation; at least some of the lowermost elevations being disposed proximate four intermediate elevations and being joined therewith by sidewalls which extend therebetween; at least some of the intermediate elevations being disposed proximate two lowermost elevations and two uppermost elevations and being joined therewith by sidewalls which extend therebetween; and at least some of the uppermost elevations being disposed proximate four intermediate elevations and being joined therewith by sidewalls which extend therebetween; forming sidewall spacers over said sidewalls, said spacers having individual lateral width dimensions; and removing material from at least one layer of the assembly, said material being disposed elevationally below at least some of the spacers, at least some of the material being selectively removed relative to material from which the spacers are formed.

Claim 56

A method of forming integrated circuitry comprising: providing a substrate; forming an assembly of layers over the substrate; defining a matrix comprising a plurality of elevational planes disposed within said assembly, said planes defining three different elevations relative to the substrate, said three different elevations comprising a lowermost elevation, an intermediate elevation, and an uppermost elevation; at least some of the lowermost elevations being disposed proximate four intermediate elevations and being joined therewith by sidewalls which extend therebetween; at least some of the intermediate elevations being disposed proximate two lowermost elevations and two uppermost elevations and being joined therewith by sidewalls which extend therebetween; and at least some of the uppermost elevations being disposed proximate four intermediate elevations and being joined therewith by sidewalls which extend therebetween; forming sidewall spacers over said sidewalls, said spacers having individual lateral width dimensions; and removing material from at least one layer of the assembly, said material being disposed elevationally below at least some of the spacers, at least some of the material being selectively removed relative to material from which the spacers are formed.