Method for fabricating local interconnect

Claim 1

A method for fabricating a local interconnect, comprising the steps of: providing a substrate; forming a patterned gate oxide layer, a patterned polysilicon layer and a patterned cap layer in sequence on the substrate, so that a gate comprising the patterned gate oxide layer, the patterned gate polysilicon layer and the patterned cap layer is formed; forming a spacer on the sidewall of the gate; forming a source/drain region in the substrate; forming a planarized dielectric layer over the substrate, wherein the planarized dielectric layer exposes the cap layer; removing a portion of the dielectric layer and the spacer on one side of the gate to form an opening, so that the source/drain region is exposed; removing the cap layer to transform the opening into a local-interconnect opening; and forming a conductive layer in the local-interconnect opening to form a local interconnect.

Claim 2

A method for fabricating a local interconnect, comprising the steps of: providing a substrate; forming a patterned gate oxide layer, a patterned polysilicon layer and a patterned cap layer in sequence on the substrate, so that a gate comprising the patterned gate oxide layer, the patterned gate polysilicon layer and the patterned cap layer is formed; forming a spacer on the sidewall of the gate; forming a source/drain region in the substrate; forming a planarized dielectric layer over the substrate, wherein the planarized dielectric layer exposes the cap layer; removing a portion of the dielectric layer and the spacer on one side of the gate to form an opening, so that the source/drain region is exposed; removing the cap layer to transform the opening into a local-interconnect opening; and forming a conductive layer in the local-interconnect opening to form a local interconnect.

Claim 12

A method for fabricating a local interconnect, comprising the steps of: providing a substrate; forming an isolation region in the substrate to define a first active region and a second active region; forming a first gate and a second gate in the first active region and the second active region, respectively, wherein the first gate comprises a first gate oxide layer, a first gate polysilicon layer and a first cap layer and the second gate comprises a second gate oxide layer, a second gate polysilicon layer and a second cap layer; forming a first spacer and a second spacer on the sidewall of the first gate and the second gate, respectively; forming a first source/drain region and a second source/drain region in the first active region and the second active region, respectively; forming a planarized dielectric layer over the substrate, wherein the planarized dielectric layer exposes the first cap layer and the second cap layer; removing a portion of the dielectric layer and the second spacer on one side of the second gate to form a first opening, wherein the second source/drain region is exposed; removing the first cap layer and the second cap layer, so that a second opening is formed to expose the second gate polysilicon layer and the first opening is transformed into a local-interconnect opening; and filling the second opening and the local-interconnect opening with a conductive layer, so that a gate conductive layer and a local interconnect are formed.

Claim 13

A method for fabricating a local interconnect, comprising the steps of: providing a substrate; forming an isolation region in the substrate to define a first active region and a second active region; forming a first gate and a second gate in the first active region and the second active region, respectively, wherein the first gate comprises a first gate oxide layer, a first gate polysilicon layer and a first cap layer and the second gate comprises a second gate oxide layer, a second gate polysilicon layer and a second cap layer; forming a first spacer and a second spacer on the sidewall of the first gate and the second gate, respectively; forming a first source/drain region and a second source/drain region in the first active region and the second active region, respectively; forming a planarized dielectric layer over the substrate, wherein the planarized dielectric layer exposes the first cap layer and the second cap layer; removing a portion of the dielectric layer and the second spacer on one side of the second gate to form a first opening, wherein the second source/drain region is exposed; removing the first cap layer and the second cap layer, so that a second opening is formed to expose the second gate polysilicon layer and the first opening is transformed into a local-interconnect opening; and filling the second opening and the local-interconnect opening with a conductive layer, so that a gate conductive layer and a local interconnect are formed.