US5773310A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating a MOS transistor
Assignee: SK Hynix Inc
•
Filing: 1995-07-19
•
Granted: 1998-06-30
•
Expires: 2015-07-19
Abstract
Abstract A transistor fabricated by a characteristic method which comprises forming a source/drain region prior to the formation of a gate electrode and then, forming source/drain pads which are in contact with the source/drain and insulated from the gate electrode, comprising a MOSFET structure in which two identical conductors are a predetermined distance away from each other on a semiconductor substrate beneath each of which a source/drain diffusion region is formed in electrical connection with it and between which a gate oxide film is formed on the semiconductor substrate, and a gate electrode extends over the two separated connectors while being insulated therefrom. It secures enough mask alignment allowance and is widely applied not only to transistors but also to DRAMs or SRAMs.
Inventors
- 👤 Sung Wook Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 13:00
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/05; H10B12/30; H10B12/31; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0273; H10D64/00; H10D64/01; H10D64/017; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/018; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
254 words
A method for fabricating a transistor, comprising the steps of: (a) depositing a first insulating film on a semiconductor substrate of a first conductivity type; (b) selectively etching the first insulating film to form a contact hole in the first insulating film, wherein a portion of the semiconductor substrate is exposed through the contact hole, forming an exposed area of the semiconductor substrate for source/drain; (c) implanting dopants into the exposed area of the semiconductor substrate to form source/drain diffusion regions, the dopants having a second conductivity type that is different from the first conductivity type of the semiconductor substrate; (d) filling the contact hole with a conductive material, to form a conductor therein; (e) subjecting the first insulating film to dry etch to form first insulating film spacers at the sidewalls of the conductor; (f) forming a gate oxide film and a conductor oxide film on the semiconductor substrate and the conductor, respectively; (g) depositing a conductive layer for a gate electrode and a second insulating film, in sequence, on the structure formed in step (f); (h) selectively etching the conductive layer and the second insulating film by use of a gate electrode mask, to form a gate electrode and a second insulating film pattern; (i) forming a third insulating film spacer at the sidewall of the gate electrode; (j) etching the conductor oxide film on the top of the conductor to expose the conductor; and (k) forming a source/drain pad that is connected to the conductor and insulated from the gate electrode.
Claim 2
Independent Claim
254 words
A method for fabricating a transistor, comprising the steps of: (a) depositing a first insulating film on a semiconductor substrate of a first conductivity type; (b) selectively etching the first insulating film to form a contact hole in the first insulating film, wherein a portion of the semiconductor substrate is exposed through the contact hole, forming an exposed area of the semiconductor substrate for source/drain; (c) implanting dopants into the exposed area of the semiconductor substrate to form source/drain diffusion regions, the dopants having a second conductivity type that is different from the first conductivity type of the semiconductor substrate; (d) filling the contact hole with a conductive material, to form a conductor therein; (e) subjecting the first insulating film to dry etch to form first insulating film spacers at the sidewalls of the conductor; (f) forming a gate oxide film and a conductor oxide film on the semiconductor substrate and the conductor, respectively; (g) depositing a conductive layer for a gate electrode and a second insulating film, in sequence, on the structure formed in step (f); (h) selectively etching the conductive layer and the second insulating film by use of a gate electrode mask, to form a gate electrode and a second insulating film pattern; (i) forming a third insulating film spacer at the sidewall of the gate electrode; (j) etching the conductor oxide film on the top of the conductor to expose the conductor; and (k) forming a source/drain pad that is connected to the conductor and insulated from the gate electrode.
Claim 3
Dependent Claim
22 words
A method in accordance with claim 1, wherein the gate oxide film and the conductor oxide film are formed by thermal oxidation.
Claim 4
Dependent Claim
61 words
A method in accordance with claim 1, further comprising the step of diffusing dopants into the semiconductor substrate to form a diffusion region in the semiconductor substrate adjacent to the source/drain diffusion region, subsequent to forming the third insulating film spacer in step (i), wherein the dopants have a conductivity type different from the first conductivity type of the semiconductor substrate.
Claim 5
Dependent Claim
47 words
A method in accordance with claim 1, wherein the conductor is formed by a selective growth process or by a process which comprises forming a conductive layer on the structure formed in step (c) and then etching the conductive layer until the first insulating film is exposed.
Claim 6
Dependent Claim
59 words
A method in accordance with claim 1, wherein step (i), formation of the third insulating film spacer, is performed after step (j), and the third insulating film spacer is formed by depositing a third insulating film over the structure formed in step (j), and subjecting the third insulating film to dry etch to form the third insulating film spacer.
Claim 7
Dependent Claim
22 words
A method in accordance with claim 1, wherein source/drain pad is formed so that it overlaps a portion of the gate electrode.
Claim 8
Dependent Claim
80 words
A method in accordance with claim 1, wherein: first and second contact holes are formed in step (b); first and second conductors are formed in the first and second contact holes, respectively, in step (d); first and second source/drain pads are formed in step (k); the first and second conductors are connected to the first and second source/drain pads, respectively; the first conductor serves as a bit line; and the second conductor serves as a storage electrode of a capacitor.
References Cited (Backward Citations)
US4722909A
Cited
US4948744A
Cited
US5141891A
Cited
US4994404A
Cited
US5240872A
Cited
US5416034A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-06-29 | 2001-12-29 | 2002-06-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-06-29 | 2005-12-29 | 2006-06-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-06-29 | 2009-12-29 | 2010-06-30 | $7700.00 | Window Closed / Lapsed |