Method of forming a field effect transistor and method of forming CMOS integrated circuitry

Claim 1

A method of forming CMOS integrated circuitry comprising the following steps: providing a series of isolation regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing a layer of polysilicon over the substrate, the polysilicon layer defining a first pair of polysilicon outward projections extending from the semiconductor substrate adjacent the first gate line, the polysilicon layer defining a second pair of polysilicon outward projections extending from the semiconductor substrate adjacent the second gate line; masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively; the polysilicon layer having not been patterned by masking between the first and second gate lines prior to the conductively doping of said other pair; masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; forming an outgassing capping layer over the first and second pairs of polysilicon outward projections; with the outgassing capping layer over the first and second pairs of polysilicon outward projections, out-diffusing n-type conductivity enhancing dopant impurity from the first pair of polysilicon projections into the semiconductor substrate to provide NMOS type diffusion regions within the substrate adjacent the first gate line; with the outgassing capping layer over the first and second pairs of polysilicon outward projections, out-diffusing p-type conductivity enhancing dopant impurity from the second pair of polysilicon projections into the semiconductor substrate to provide PMOS type diffusion regions within the substrate adjacent the second gate line.

Claim 2

A method of forming CMOS integrated circuitry comprising the following steps: providing a series of isolation regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing a layer of polysilicon over the substrate, the polysilicon layer defining a first pair of polysilicon outward projections extending from the semiconductor substrate adjacent the first gate line, the polysilicon layer defining a second pair of polysilicon outward projections extending from the semiconductor substrate adjacent the second gate line; masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively; the polysilicon layer having not been patterned by masking between the first and second gate lines prior to the conductively doping of said other pair; masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; forming an outgassing capping layer over the first and second pairs of polysilicon outward projections; with the outgassing capping layer over the first and second pairs of polysilicon outward projections, out-diffusing n-type conductivity enhancing dopant impurity from the first pair of polysilicon projections into the semiconductor substrate to provide NMOS type diffusion regions within the substrate adjacent the first gate line; with the outgassing capping layer over the first and second pairs of polysilicon outward projections, out-diffusing p-type conductivity enhancing dopant impurity from the second pair of polysilicon projections into the semiconductor substrate to provide PMOS type diffusion regions within the substrate adjacent the second gate line.

Claim 4

A method of forming CMOS integrated circuitry comprising the following steps: providing a series of isolation regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing nitride dopant masking caps over the first and second gate lines; providing oxide insulating sidewall spacers relative to the first gate line and the second gate line; depositing a layer of polysilicon over the substrate and chemical-mechanical polishing such deposited layer, the polished polysilicon layer defining a first pair of polysilicon outward projections extending from the semiconductor substrate adjacent the first gate line, the polysilicon layer defining a second pair of polysilicon outward projections extending from the semiconductor substrate adjacent the second gate line; masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively, to a dopant impurity concentration of at least 1×10 20 ions/cm 3 ; the polysilicon layer having not been patterned by masking between the first and second gate lines prior to the conductively doping of said other pair; masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively, to a dopant impurity concentration of at least 1×10 20 ions/cm 3 ; providing an outgassing capping layer over the first and second pairs of polysilicon outward projections; with the outgassing capping layer over the first and second pairs of polysilicon outward projections, out-diffusing n-type conductivity enhancing dopant impurity from the first pair of polysilicon projections into the semiconductor substrate to provide NMOS type diffusion regions within the substrate adjacent the first gate line; and with the outgassing capping layer over the first and second pairs of polysilicon outward projections, out-diffusing p-type conductivity enhancing dopant impurity from the second pair of polysilicon projections into the semiconductor substrate to provide PMOS type diffusion regions within the substrate adjacent the second gate line.

Claim 5

A method of forming CMOS integrated circuitry comprising the following steps: providing a series of isolation regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing nitride dopant masking caps over the first and second gate lines; providing oxide insulating sidewall spacers relative to the first gate line and the second gate line; depositing a layer of polysilicon over the substrate and chemical-mechanical polishing such deposited layer, the polished polysilicon layer defining a first pair of polysilicon outward projections extending from the semiconductor substrate adjacent the first gate line, the polysilicon layer defining a second pair of polysilicon outward projections extending from the semiconductor substrate adjacent the second gate line; masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively, to a dopant impurity concentration of at least 1×10 20 ions/cm 3 ; the polysilicon layer having not been patterned by masking between the first and second gate lines prior to the conductively doping of said other pair; masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively, to a dopant impurity concentration of at least 1×10 20 ions/cm 3 ; providing an outgassing capping layer over the first and second pairs of polysilicon outward projections; with the outgassing capping layer over the first and second pairs of polysilicon outward projections, out-diffusing n-type conductivity enhancing dopant impurity from the first pair of polysilicon projections into the semiconductor substrate to provide NMOS type diffusion regions within the substrate adjacent the first gate line; and with the outgassing capping layer over the first and second pairs of polysilicon outward projections, out-diffusing p-type conductivity enhancing dopant impurity from the second pair of polysilicon projections into the semiconductor substrate to provide PMOS type diffusion regions within the substrate adjacent the second gate line.

Claim 8

A method of forming CMOS integrated circuitry comprising the following steps: providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing a layer of polysilicon over the substrate, the polysilicon layer defining a first pair of polysilicon outward projections extending from the semiconductor substrate adjacent the first gate line, the polysilicon layer defining a second pair of polysilicon outward projections extending from the semiconductor substrate adjacent the second gate line; blanket doping the first and second pair of polysilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity, the blanket doping being conducted to a first impurity concentration; masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; the masked doping being conducted to a second impurity concentration which is greater that the first impurity concentration, wherein the masked doping step is conducted before the blanket doping step; out-diffusing n-type conductivity enhancing dopant impurity from the first pair of polysilicon projections into the semiconductor substrate to provide NMOS type diffusion regions within the substrate adjacent the first gate line; and out-diffusing p-type conductivity enhancing dopant impurity from the second pair of polysilicon projections into the semiconductor substrate to provide PMOS type diffusion regions within the substrate adjacent the second gate line.

Claim 9

A method of forming CMOS integrated circuitry comprising the following steps: providing a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing a layer of polysilicon over the substrate, the polysilicon layer defining a first pair of polysilicon outward projections extending from the semiconductor substrate adjacent the first gate line, the polysilicon layer defining a second pair of polysilicon outward projections extending from the semiconductor substrate adjacent the second gate line; blanket doping the first and second pair of polysilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity, the blanket doping being conducted to a first impurity concentration; masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; the masked doping being conducted to a second impurity concentration which is greater that the first impurity concentration, wherein the masked doping step is conducted before the blanket doping step; out-diffusing n-type conductivity enhancing dopant impurity from the first pair of polysilicon projections into the semiconductor substrate to provide NMOS type diffusion regions within the substrate adjacent the first gate line; and out-diffusing p-type conductivity enhancing dopant impurity from the second pair of polysilicon projections into the semiconductor substrate to provide PMOS type diffusion regions within the substrate adjacent the second gate line.