US5571733A
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Method of forming CMOS integrated circuitry
Assignee: Micron Technology Inc
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Filing: 1995-05-12
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Granted: 1996-11-05
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Expires: 2015-05-12
Abstract
Abstract A method of forming CMOS integrated circuitry includes, a) providing a series of field oxide regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned for formation of an NMOS transistor, a second gate line being positioned for formation of a PMOS transistor; b) providing a layer of polysilicon to define a first and second pairs of polysilicon outward projections extending from the semiconductor substrate adjacent the first and second gate lines, respectively; c) masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively; d) masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; e) out-diffusing conductivity enhancing dopant impurity from the respective pairs of polysilicon projections into the semiconductor substrate to provide respective NMOS and PMOS type diffusion regions within the substrate adjacent the respective first and second gate lines. A combination of blanket doping and masked doping to produce the respective NMOS and PMOS type diffusion regions is also contemplated. The invention also has utility to formation of only one of NMOS or PMOS type field effect transistors, as opposed to CMOS formation.
Inventors
- 👤 Jeff Z. Wu
- 👤 Sittampalam Yoganathan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 01:56
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01326; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/017; H10D84/02; H10D84/03; H10D84/038; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S148/00; Y10S148/082; Y10S148/141
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
267 words
A method of forming CMOS integrated circuitry comprising the following steps: providing a series of isolation regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing a layer of polysilicon over the substrate, the polysilicon layer defining a first pair of polysilicon outward projections extending from the semiconductor substrate adjacent the first gate line, the polysilicon layer defining a second pair of polysilicon outward projections extending from the semiconductor substrate adjacent the second gate line; masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively; the polysilicon layer having not been patterned by masking between the first and second gate lines prior to the conductively doping of said other pair; masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; out-diffusing n-type conductivity enhancing dopant impurity from the first pair of polysilicon projections into the semiconductor substrate to provide NMOS type diffusion regions within the substrate adjacent the first gate line; and out-diffusing p-type conductivity enhancing dopant impurity from the second pair of polysilicon projections into the semiconductor substrate to provide PMOS type diffusion regions within the substrate adjacent the second gate line.
Claim 2
Independent Claim
267 words
A method of forming CMOS integrated circuitry comprising the following steps: providing a series of isolation regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing a layer of polysilicon over the substrate, the polysilicon layer defining a first pair of polysilicon outward projections extending from the semiconductor substrate adjacent the first gate line, the polysilicon layer defining a second pair of polysilicon outward projections extending from the semiconductor substrate adjacent the second gate line; masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively; the polysilicon layer having not been patterned by masking between the first and second gate lines prior to the conductively doping of said other pair; masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; out-diffusing n-type conductivity enhancing dopant impurity from the first pair of polysilicon projections into the semiconductor substrate to provide NMOS type diffusion regions within the substrate adjacent the first gate line; and out-diffusing p-type conductivity enhancing dopant impurity from the second pair of polysilicon projections into the semiconductor substrate to provide PMOS type diffusion regions within the substrate adjacent the second gate line.
Claim 3
Dependent Claim
17 words
The method of forming CMOS integrated circuitry of claim 1 wherein the out-diffusing steps are conducted simultaneously.
Claim 4
Dependent Claim
24 words
The method of forming CMOS integrated circuitry of claim 1 wherein the isolation regions are provided to be recessed relative to the semiconductor substrate.
Claim 5
Dependent Claim
37 words
The method of forming CMOS integrated circuitry of claim 1 wherein the step of providing the polysilicon layer comprises depositing a layer of polysilicon and chemical-mechanical polishing such deposited layer prior to the masking and doping steps.
Claim 6
Dependent Claim
30 words
The method of forming CMOS integrated circuitry of claim 1 further comprising providing dopant masking caps over the first and second gate lines prior to the masking and doping steps.
Claim 7
Dependent Claim
32 words
The method of forming CMOS integrated circuitry of claim 1 further comprising providing an outgassing capping layer over the first and second pairs of polysilicon outward projections prior to the out-diffusing steps.
Claim 8
Dependent Claim
47 words
The method of forming CMOS integrated circuitry of claim 1 further comprising: providing dopant masking caps over the first and second gate lines prior to the masking and doping steps; and providing an out gassing capping layer over the first and second pairs of polysilicon outward projections.
Claim 9
Dependent Claim
48 words
The method of forming CMOS integrated circuitry of claim 1 further comprising providing nitride dopant masking caps over the first and second gate lines prior to the masking and doping steps, and providing oxide insulating sidewall spacers relative to the first gate line and the second gate line.
Claim 10
Dependent Claim
36 words
The method of forming CMOS integrated circuitry of claim 1 wherein the polysilicon layer has not been patterned by masking between the first and second gate lines prior to the conductively doping of said one pair.
Claim 11
Dependent Claim
42 words
The method of forming CMOS integrated circuitry of claim 1 wherein at least one of the projections of the first pair is continuous with at least one of the projections of the second pair during the conductively doping of said other pair.
Claim 12
Dependent Claim
42 words
The method of forming CMOS integrated circuitry of claim 1 wherein at least one of the projections of the first pair is continuous with at least one of the projections of the second pair during the conductively doping of said one pair.
Claim 13
Dependent Claim
47 words
The method of forming CMOS integrated circuitry of claim 1 wherein at least one of the projections of the first pair is continuous with at least one of the projections of the second pair during the conductively dopings of both said other pair and said one pair.
Claim 14
Independent Claim
355 words
A method of forming CMOS integrated circuitry comprising the following steps: providing a series of isolation regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing nitride dopant masking caps over the first and second gate lines; providing oxide insulating sidewall spacers relative to the first gate line and the second gate line; depositing a layer of polysilicon over the substrate and chemical-mechanical polishing such deposited layer, the polished polysilicon layer defining a first pair of polysilicon outward projections extending from the semiconductor substrate adjacent the first gate line, the polysilicon layer defining a second pair of polysilicon outward projections extending from the semiconductor substrate adjacent the second gate line; masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively, to a dopant impurity concentration of at least 1×10 20 ions/cm 3 ; the polysilicon layer having not been patterned by masking between the first and second gate lines prior to the conductively doping of said other pair; masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively, to a dopant impurity concentration of at least 1×10 20 ions/cm 3 ; providing an outgassing capping layer over the first and second pairs of polysilicon outward projections; after providing the outgassing capping layer, out-diffusing n-type conductivity enhancing dopant impurity from the first pair of polysilicon projections into the semiconductor substrate to provide NMOS type diffusion regions within the substrate adjacent the first gate line; and after providing the outgassing capping layer, out-diffusing p-type conductivity enhancing dopant impurity from the second pair of polysilicon projections into the semiconductor substrate to provide PMOS type diffusion regions within the substrate adjacent the second gate line.
Claim 15
Independent Claim
355 words
A method of forming CMOS integrated circuitry comprising the following steps: providing a series of isolation regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing nitride dopant masking caps over the first and second gate lines; providing oxide insulating sidewall spacers relative to the first gate line and the second gate line; depositing a layer of polysilicon over the substrate and chemical-mechanical polishing such deposited layer, the polished polysilicon layer defining a first pair of polysilicon outward projections extending from the semiconductor substrate adjacent the first gate line, the polysilicon layer defining a second pair of polysilicon outward projections extending from the semiconductor substrate adjacent the second gate line; masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair with an n-type or a p-type conductivity enhancing dopant impurity, respectively, to a dopant impurity concentration of at least 1×10 20 ions/cm 3 ; the polysilicon layer having not been patterned by masking between the first and second gate lines prior to the conductively doping of said other pair; masking the other of the first or second pair of polysilicon projections while conductively doping the one of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively, to a dopant impurity concentration of at least 1×10 20 ions/cm 3 ; providing an outgassing capping layer over the first and second pairs of polysilicon outward projections; after providing the outgassing capping layer, out-diffusing n-type conductivity enhancing dopant impurity from the first pair of polysilicon projections into the semiconductor substrate to provide NMOS type diffusion regions within the substrate adjacent the first gate line; and after providing the outgassing capping layer, out-diffusing p-type conductivity enhancing dopant impurity from the second pair of polysilicon projections into the semiconductor substrate to provide PMOS type diffusion regions within the substrate adjacent the second gate line.
Claim 16
Dependent Claim
24 words
The method of forming CMOS integrated circuitry of claim 13 wherein the isolation regions are provided to be recessed relative to the semiconductor substrate.
Claim 17
Dependent Claim
17 words
The method of forming CMOS integrated circuitry of claim 13 wherein the out-diffusing steps are conducted simultaneously.
Claim 18
Dependent Claim
28 words
The method of forming CMOS integrated circuitry of claim 13 wherein the chemical-mechanical polishing step comprises using the nitride dopant masking caps as a chemical-mechanical polishing etch stop.
Claim 19
Dependent Claim
36 words
The method of forming CMOS integrated circuitry of claim 13 wherein the polysilicon layer has not been patterned by masking between the first and second gate lines prior to the conductively doping of said one pair.
Claim 20
Dependent Claim
42 words
The method of forming CMOS integrated circuitry of claim 13 wherein at least one of the projections of the first pair is continuous with at least one of the projections of the second pair during the conductively doping of said other pair.
Claim 21
Dependent Claim
42 words
The method of forming CMOS integrated circuitry of claim 13 wherein at least one of the projections of the first pair is continuous with at least one of the projections of the second pair during the conductively doping of said one pair.
Claim 22
Dependent Claim
47 words
The method of forming CMOS integrated circuitry of claim 13 wherein at least one of the projections of the first pair is continuous with at least one of the projections of the second pair during the conductively dopings of both said other pair and said one pair.
Claim 23
Independent Claim
259 words
A method of forming CMOS integrated circuitry comprising the following steps: providing a series of field oxide regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing a layer of polysilicon over the substrate, the polysilicon layer defining a first pair of polysilicon outward projections extending from the semiconductor substrate adjacent the first gate line, the polysilicon layer defining a second pair of polysilicon outward projections extending from the semiconductor substrate adjacent the second gate line; blanket doping the first and second pair of polysilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity, the blanket doping being conducted to a first impurity concentration; masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; the masked doping being conducted to a second impurity concentration which is greater that the first impurity concentration; out-diffusing n-type conductivity enhancing dopant impurity from the first pair of polysilicon projections into the semiconductor substrate to provide NMOS type diffusion regions within the substrate adjacent the first gate line; and out-diffusing p-type conductivity enhancing dopant impurity from the second pair of polysilicon projections into the semiconductor substrate to provide PMOS type diffusion regions within the substrate adjacent the second gate line.
Claim 24
Independent Claim
259 words
A method of forming CMOS integrated circuitry comprising the following steps: providing a series of field oxide regions and a series of gate lines over a semiconductor substrate, a first gate line being positioned relative to the substrate for formation of an NMOS transistor, a second gate line being positioned relative to the substrate for formation of a PMOS transistor; providing a layer of polysilicon over the substrate, the polysilicon layer defining a first pair of polysilicon outward projections extending from the semiconductor substrate adjacent the first gate line, the polysilicon layer defining a second pair of polysilicon outward projections extending from the semiconductor substrate adjacent the second gate line; blanket doping the first and second pair of polysilicon projections with one of an n-type or a p-type conductivity enhancing dopant impurity, the blanket doping being conducted to a first impurity concentration; masking one of the first or second pair of polysilicon projections while conductively doping the other of the first or second pair of polysilicon projections with an n-type or a p-type conductivity enhancing dopant impurity, respectively; the masked doping being conducted to a second impurity concentration which is greater that the first impurity concentration; out-diffusing n-type conductivity enhancing dopant impurity from the first pair of polysilicon projections into the semiconductor substrate to provide NMOS type diffusion regions within the substrate adjacent the first gate line; and out-diffusing p-type conductivity enhancing dopant impurity from the second pair of polysilicon projections into the semiconductor substrate to provide PMOS type diffusion regions within the substrate adjacent the second gate line.
Claim 25
Dependent Claim
22 words
The method of forming CMOS integrated circuitry of claim 21 wherein the blanket doping step is conducted before the masked doping step.
Claim 26
Dependent Claim
22 words
The method of forming CMOS integrated circuitry of claim 21 wherein the masked doping step is conducted before the blanket doping step.
Claim 27
Dependent Claim
17 words
The method of forming CMOS integrated circuitry of claim 21 wherein the out-diffusing steps are conducted simultaneously.
Claim 28
Dependent Claim
31 words
The method of forming CMOS integrated circuitry of claim 21 further comprising providing dopant masking caps over the first and second gate lines prior to the blanket and masked doping steps.
Claim 29
Dependent Claim
32 words
The method of forming CMOS integrated circuitry of claim 21 further comprising providing an outgassing capping layer over the first and second pairs of polysilicon outward projections prior to the out-diffusing steps.
Claim 30
Dependent Claim
47 words
The method of forming CMOS integrated circuitry of claim 21 further comprising: providing dopant masking caps over the first and second gate lines prior to the blanket and masked doping steps; and providing an outgassing capping layer over the first and second pairs of polysilicon outward projections.
References Cited (Backward Citations)
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| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
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