Patent US6083805A successfully refreshed from Google Patents.
US6083805A
Expired / Lapsed
US
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Method of forming capacitors in a semiconductor device
Assignee: Teledyne Digital Imaging Inc
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Filing: 1999-05-19
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Granted: 2000-07-04
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Expires: 2019-05-19
Abstract
Abstract A method of forming capacitors in a semiconductor device, involves providing a first insulating layer, providing a first mask with an array of apertures over the insulating layer, and etching an array of holes in the first insulating layer through said apertures in said first mask. A first electrode layer extending into the holes is formed over the first insulating layer. A second dielectric layer extends into the holes on said first electrode layer. A second electrode layer extends into the holes on the dielectric layer. The capacitors are patterned with a second mask. The capacitors can be subsequently connected into the circuit in a sequence of processing steps that only involve the addition two extra masks beyond those conventionally employed in integrated circuit manufacture.
Inventors
- 👤 Luc Ouellet
- 👤 Stephane Blain
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:55
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10D84/00; H10D84/80; H10D84/811; H10D84/813
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
236 words
A method of making a semiconductor device with capacitors, comprising the steps of: a) providing a first insulating layer on a wafer; b) providing a first mask with an array of apertures over said insulating layer; c) etching an array of holes in said first insulating layer through said apertures in said first mask; d) forming a first electrode layer extending into said holes over said first insulating layer; e) forming a dielectric layer extending into said holes on said first electrode layer; f) forming a second electrode layer extending into said holes on said dielectric layer; g) patterning said second electrode layer, said dielectric layer and said first electrode layer with a second mask to form said capacitors; h) depositing an isolation layer on said wafer over said second electrode layer to isolate the edges of said first and second electrode layers; i) etching first via holes through said isolation layer and first insulating layer to reach active components in the wafer; j) applying a first metal layer over said isolation layer and said first insulating layer to contact said active components through said first via holes; k) applying a second insulating layer over said first metal layer; l) etching second via holes through said second insulating layer to reach said second electrode layer of said capacitors; and m) applying a second metal layer to contact said second electrode layer through said second via holes.
Claim 2
Independent Claim
236 words
A method of making a semiconductor device with capacitors, comprising the steps of: a) providing a first insulating layer on a wafer; b) providing a first mask with an array of apertures over said insulating layer; c) etching an array of holes in said first insulating layer through said apertures in said first mask; d) forming a first electrode layer extending into said holes over said first insulating layer; e) forming a dielectric layer extending into said holes on said first electrode layer; f) forming a second electrode layer extending into said holes on said dielectric layer; g) patterning said second electrode layer, said dielectric layer and said first electrode layer with a second mask to form said capacitors; h) depositing an isolation layer on said wafer over said second electrode layer to isolate the edges of said first and second electrode layers; i) etching first via holes through said isolation layer and first insulating layer to reach active components in the wafer; j) applying a first metal layer over said isolation layer and said first insulating layer to contact said active components through said first via holes; k) applying a second insulating layer over said first metal layer; l) etching second via holes through said second insulating layer to reach said second electrode layer of said capacitors; and m) applying a second metal layer to contact said second electrode layer through said second via holes.
Claim 3
Dependent Claim
17 words
A method as claimed in claim 1, wherein said dielectric layer is formed in a separate chamber.
Claim 4
Dependent Claim
16 words
A method as claimed in claim 2, wherein said dielectric layer is formed by furnace oxidation.
Claim 5
Dependent Claim
16 words
A method as claimed in claim 3, wherein said dielectric layer is formed by plasma oxidation.
Claim 6
Dependent Claim
17 words
A method as claimed in claim 3, wherein said dielectric layer is formed by rapid thermal oxidation.
Claim 7
Dependent Claim
26 words
A method as claimed in claim 3, wherein an initial seed layer is formed by partial oxidation of the first electrode using an integrated oxygen plasma.
Claim 8
Dependent Claim
18 words
A method as claimed in claim 1, wherein said first and second metal layers are patterned after deposition.
Claim 9
Dependent Claim
16 words
A method as claimed in claim 1, wherein said first insulating layer is a composite layer.
Claim 10
Dependent Claim
13 words
A method as claimed in claim 1, wherein said composite layer comprises SG/PSG/SOG.
Claim 11
Dependent Claim
31 words
A method as claimed in claim 9, wherein said PSG contains about 4 wt. % of phosphorus and said SOG is an inorganic SOG containing about 4 wt. % of phosphorus.
Claim 12
Dependent Claim
18 words
A method as claimed in claim 1 to, wherein said first electrode layer comprises a Ti/TiN composite layer.
Claim 13
Dependent Claim
17 words
A method as claimed in claim 1, wherein said second electrode layer comprises a TiN/Ti/TiN composite layer.
Claim 14
Dependent Claim
14 words
A method as claimed in claim 1, wherein said dielectric layer is titanium oxide.
Claim 15
Dependent Claim
14 words
A method as claimed in claim 1, wherein said dielectric layer is silicon nitride.
Claim 16
Dependent Claim
25 words
A method as claimed in claim 1, wherein said dielectric layer is a composite layer comprising a titanium oxide sublayer and a silicon nitride sublayer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-04 | 2004-01-03 | 2004-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-04 | 2008-01-03 | 2008-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-04 | 2012-01-03 | 2012-07-04 | $7700.00 | Window Closed / Lapsed |