Multiple step ionized metal plasma deposition process for conformal step coverage

Claim 2

A multiple step process for sputter depositing a material of uniform thickness over a stepped surface of an integrated circuit structure on a semiconductor substrate on a support pedestal in a sputter deposition chamber having a sputtering target and an RF coil therein for coupling RF energy to a plasma maintained between the target and the support pedestal which comprises: a) in a first sputter deposition step, sputter depositing material from said target onto at least a lowest region of said stepped surface while: i) maintaining said chamber at a high pressure; ii) providing a high power RF energy to said coil in said deposition chamber; iii) applying a high power RF bias to said pedestal supporting said substrate being deposited upon; and iv) applying a low power DC bias to said sputtering target; b) then, in a second, sputter deposition step, reducing said high power RF bias on said pedestal to a lower power while continuing to deposit on said stepped surface, to thereby deposit at least on a first higher region of said stepped surface; c) then, in a third sputter deposition step, applying no RF bias to said pedestal and reducing said pressure in said sputtering chamber to a medium pressure, while continuing to deposit on said stepped surface, to thereby deposit material on at least a second higher region of said stepped surface; d) then, in a fourth sputter deposition step, reducing said high power RF energy to said coil to low power RF energy while continuing to deposit on said stepped surface, to thereby deposit material on at least a third higher region of said stepped surface; and e) then, in a fifth sputter deposition step, lowering said pressure in said chamber further to a low pressure state and applying a high power DC bias to said target, while continuing to deposit material on said stepped surface, to thereby deposit material on at least a highest region of said stepped surface; whereby a uniform thickness of material is sputtered onto said stepped surface.

Claim 3

The process of claim 1 wherein said sputtering chamber is maintained at a high pressure of at least 35 millitorr during said first and second sputter deposition steps.

Claim 4

The process of claim 1 wherein said sputtering chamber is maintained at a medium pressure of from 10 millitorr to below 35 millitorr during said third and fourth sputter deposition steps.

Claim 5

The process of claim 1 wherein said sputtering chamber is maintained at a low pressure of below 10 millitorr during said fifth sputter deposition step.

Claim 6

The process of claim 1 wherein said high power RF energy to said coil is maintained at a power level of at least about 4 kilowatts (kw) during said first, second, and third sputter deposition steps.

Claim 7

The process of claim 1 wherein said low power RF energy to said coil is maintained at a power level of not greater than about 3 kilowatts (kw) during said fourth and fifth sputter deposition steps.

Claim 8

The process of claim 1 wherein said high power RF bias on said pedestal is maintained at a power level of at least about 400 watts during said first sputter deposition step.

Claim 9

The process of claim 1 wherein said low power RF bias on said pedestal is maintained at a power level of from about 100 watts to about 200 watts during said second sputter deposition step.

Claim 10

The process of claim 1 wherein said RF bias on said pedestal is maintained at a power level of 400 watts during said first deposition step, and is ramped down during said second sputter deposition step to reach a level of zero at the commencement of said third deposition step.

Claim 11

The process of claim 1 wherein said low power DC target power is maintained at a power level of not greater than 3 kw during said first four sputter deposition steps.

Claim 12

The process of claim 1 wherein said high power DC target power is maintained at a power level greater than 3 kw during said fifth sputter deposition step.

Claim 13

The process of claim 1 wherein one or more of said sputter deposition steps are carried out in a first sputter deposition chamber and one or more of said sputter deposition steps are carried out in a second deposition chamber.

Claim 14

A multiple step process for sputter depositing a material of uniform thickness over a stepped surface of an integrated circuit structure on a semiconductor substrate on a support pedestal in a sputter deposition chamber having a sputtering target and an RF coil therein for coupling RF energy to a plasma maintained between the target and the support pedestal which comprises: a) in a first deposition step, sputter depositing material from said target onto at least a lowest region of said stepped surface while: i) maintaining said chamber at a high pressure of at least 35 millitorr; ii) providing a high power RF energy of at least about 4 kilowatts (kw) to said coil in said deposition chamber; iii) applying a high power RF bias of at least about 400 watts to said pedestal supporting said substrate being deposited upon; and iv) applying a low power DC bias of not greater than 3 kw to said sputtering target; b) then, in a second deposition step, reducing said high power RF bias on said pedestal to a lower power of from about 100 watts to about 200 watts while continuing to deposit on said stepped surface, by maintaining said high pressure in said chamber and while maintaining said low power DC bias on said target and said high power RF energy to said coil, to thereby deposit on a first higher region of said stepped surface; c) then, in a third deposition step, applying no RF bias to said pedestal and reducing said pressure in said sputtering chamber to a medium pressure of from 10 millitorr to below 35 millitorr, while continuing to deposit on said stepped surface by maintaining said low power DC bias on said target and said high power RF energy to said coil to thereby deposit material on a second higher region of said stepped surface; d) then, in a fourth deposition step, reducing said high power RF energy to said coil to low power RF energy of not greater than about 3 kw, while continuing to deposit on said stepped surface, by continuing to maintain said pressure in said chamber at said medium level and said DC bias on said target at a low power, with no RF bias applied to said pedestal to thereby deposit material on a third higher region of said stepped surface; and e) then, in a fifth deposition step, lowering said pressure in said chamber further to a low pressure state of below 10 millitorr and applying a high power DC bias to said target of greater than 3 kw, while continuing to deposit material on said stepped surface by maintaining said RF energy to said coil at a low power level and no RF bias applied to said pedestal, to thereby deposit material on a highest region of said stepped surface; whereby a uniform thickness of material is sputtered onto substantially all of said stepped surface.

Claim 15

A multiple step process for sputter depositing a material of uniform thickness over a stepped surface of an integrated circuit structure on a semiconductor substrate on a support pedestal in a sputter deposition chamber having a sputtering target and an RF coil therein for coupling RF energy to a plasma maintained between the target and the support pedestal which comprises: a) in a first deposition step, sputter depositing material from said target onto at least a lowest region of said stepped surface while: i) maintaining said chamber at a high pressure of at least 35 millitorr; ii) providing a high power RF energy of at least about 4 kilowatts (kw) to said coil in said deposition chamber; iii) applying a high power RF bias of at least about 400 watts to said pedestal supporting said substrate being deposited upon; and iv) applying a low power DC bias of not greater than 3 kw to said sputtering target; b) then, in a second deposition step, reducing said high power RF bias on said pedestal to a lower power of from about 100 watts to about 200 watts while continuing to deposit on said stepped surface, by maintaining said high pressure in said chamber and while maintaining said low power DC bias on said target and said high power RF energy to said coil, to thereby deposit on a first higher region of said stepped surface; c) then, in a third deposition step, applying no RF bias to said pedestal and reducing said pressure in said sputtering chamber to a medium pressure of from 10 millitorr to below 35 millitorr, while continuing to deposit on said stepped surface by maintaining said low power DC bias on said target and said high power RF energy to said coil to thereby deposit material on a second higher region of said stepped surface; d) then, in a fourth deposition step, reducing said high power RF energy to said coil to low power RF energy of not greater than about 3 kw, while continuing to deposit on said stepped surface, by continuing to maintain said pressure in said chamber at said medium level and said DC bias on said target at a low power, with no RF bias applied to said pedestal to thereby deposit material on a third higher region of said stepped surface; and e) then, in a fifth deposition step, lowering said pressure in said chamber further to a low pressure state of below 10 millitorr and applying a high power DC bias to said target of greater than 3 kw, while continuing to deposit material on said stepped surface by maintaining said RF energy to said coil at a low power level and no RF bias applied to said pedestal, to thereby deposit material on a highest region of said stepped surface; whereby a uniform thickness of material is sputtered onto substantially all of said stepped surface.

Claim 16

The process of claim 13 where said first and second deposition steps are carried out for the same length of time to provide for uniformity of thickness in material deposited during said first and second deposition steps.

Claim 17

The process of claim 14 wherein said third and fourth deposition steps are carried out for the same length of time and the deposition time for said third and fourth deposition steps are from about 1/2 to about 3/4 of the deposition time of said first and second deposition steps to provide for uniformity of thickness in material deposited during said first, second, third, and fourth deposition steps.

Claim 18

The process of claim 15 wherein the deposition time of said fifth deposition step is from about 1/8 to about 3/8 of the deposition time of said first and second deposition steps to provide for uniformity of thickness in material deposited during said five deposition steps.

Claim 19

The process of claim 15 wherein the deposition time of said fifth deposition step is about 1/4 of the deposition time of said first and second deposition steps to provide for uniformity of thickness in material deposited during said five deposition steps.

Claim 20

The process of claim 14 wherein said third and fourth deposition steps are carried out for the same length of time and the deposition time for said third and fourth deposition steps are about 5/8 of the deposition time of said first and second deposition steps to provide for uniformity of thickness in material deposited during said first, second, third, and fourth deposition steps.

Claim 21

A multiple step process for sputter depositing a material of uniform thickness onto bottom and sidewall surfaces of a high aspect ratio opening formed through an insulating layer of an integrated circuit structure on a semiconductor substrate mounted on a support pedestal in a sputter deposition chamber having a sputtering target and an RF coil therein for coupling RF energy to a plasma maintained between the target and the support pedestal which comprises: a) in a first deposition step, sputter depositing material from said target onto at least the bottom surface of said high aspect ratio opening while: i) maintaining said chamber at a high pressure of at least 35 millitorr; ii) providing a high power RF energy of at least about 4 kilowatts (kw) to said coil in said deposition chamber; iii) applying a high power RF bias of at least about 400 watts to said pedestal supporting said substrate being deposited upon; and iv) applying a low power DC bias of not greater than 3 kw to said sputtering target; b) then, in a second deposition step, reducing said high power RF bias on said pedestal to a lower power by ramping said RF bias down to a level of zero at the end of said second deposition step, while maintaining said high pressure in said chamber and while maintaining said low power DC bias on said target and said high power RF energy to said coil, to thereby deposit material on at least a lowest quartile of said sidewall surface; c) then, in a third deposition step, applying no RF bias to said pedestal and reducing said pressure in said sputtering chamber to a medium pressure of from 10 millitorr to below 35 millitorr, while maintaining said low power DC bias on said target and said high RF power to said coil, to thereby deposit material on at least a second quartile of said sidewall surface; d) then, in a fourth deposition step, reducing said high power RF energy to said coil to low power RF energy of not greater than about 3 kw, while maintaining said pressure at said medium level and said DC bias on said target at a low state, with no RF bias applied to said pedestal to thereby deposit material on at least a third quartile of said sidewall surface; and e) then, in a fifth deposition step, lowering said chamber pressure further to a low pressure state of below 10 millitor and applying a high power DC bias of greater than 3 kw to said target, while maintaining said RF energy to said coil at said low power level and no RF bias applied to said pedestal, to thereby deposit material on at least a fourth quartile of said sidewall surface; whereby a uniform thickness of material is sputtered onto substantially all of said bottom and sidewall surfaces of said high aspect ratio opening in said integrated circuit structure.

Claim 22

A multiple step process for sputter depositing a material of uniform thickness onto bottom and sidewall surfaces of a high aspect ratio opening formed through an insulating layer of an integrated circuit structure on a semiconductor substrate mounted on a support pedestal in a sputter deposition chamber having a sputtering target and an RF coil therein for coupling RF energy to a plasma maintained between the target and the support pedestal which comprises: a) in a first deposition step, sputter depositing material from said target onto at least the bottom surface of said high aspect ratio opening while: i) maintaining said chamber at a high pressure of at least 35 millitorr; ii) providing a high power RF energy of at least about 4 kilowatts (kw) to said coil in said deposition chamber; iii) applying a high power RF bias of at least about 400 watts to said pedestal supporting said substrate being deposited upon; and iv) applying a low power DC bias of not greater than 3 kw to said sputtering target; b) then, in a second deposition step, reducing said high power RF bias on said pedestal to a lower power by ramping said RF bias down to a level of zero at the end of said second deposition step, while maintaining said high pressure in said chamber and while maintaining said low power DC bias on said target and said high power RF energy to said coil, to thereby deposit material on at least a lowest quartile of said sidewall surface; c) then, in a third deposition step, applying no RF bias to said pedestal and reducing said pressure in said sputtering chamber to a medium pressure of from 10 millitorr to below 35 millitorr, while maintaining said low power DC bias on said target and said high RF power to said coil, to thereby deposit material on at least a second quartile of said sidewall surface; d) then, in a fourth deposition step, reducing said high power RF energy to said coil to low power RF energy of not greater than about 3 kw, while maintaining said pressure at said medium level and said DC bias on said target at a low state, with no RF bias applied to said pedestal to thereby deposit material on at least a third quartile of said sidewall surface; and e) then, in a fifth deposition step, lowering said chamber pressure further to a low pressure state of below 10 millitor and applying a high power DC bias of greater than 3 kw to said target, while maintaining said RF energy to said coil at said low power level and no RF bias applied to said pedestal, to thereby deposit material on at least a fourth quartile of said sidewall surface; whereby a uniform thickness of material is sputtered onto substantially all of said bottom and sidewall surfaces of said high aspect ratio opening in said integrated circuit structure.

Claim 23

The process of claim 19 wherein said sputtering chamber is maintained at a medium pressure of from 20 millitorr to about 30 millitor during said third and fourth deposition steps.

Claim 24

The process of claim 19 wherein said sputtering chamber is maintained at a low pressure of from about 1 millitor to about 5 millitorr during said fifth deposition step.

Claim 25

The process of claim 19 wherein said high power RF energy to said coil is maintained at a power level of from at least about 4 kw to about 5 kw during said first, second, and third deposition steps.

Claim 26

The process of claim 19 wherein said low power RF energy to said coil is maintained at a power level of from about 1 kw to about 3 kw during said fourth and fifth deposition steps.

Claim 27

The process of claim 19 wherein said high power DC target power maintained at a power level of at least about 5 kw during said fifth deposition step.

Claim 28

The process of claim 19 wherein the material sputtered onto the bottom and sidewall surfaces of said opening is selected from the group consisting of titanium, titanium nitride, tantalum nitride, tungsten nitride, and copper.

Claim 29

The process of claim 19 where said first and second deposition steps are carried out for the same length of time to provide for uniformity of thickness in material deposited during said first and second deposition steps.

Claim 30

The process of claim 19 wherein said third and fourth deposition steps are carried out for the same length of time and the deposition time for said third and fourth deposition steps are from about 1/2 to about 3/4 of the deposition time of said first and second deposition steps to provide for uniformity of thickness in material deposited during said first, second, third, and fourth deposition steps.

Claim 31

The process of claim 19 wherein said third and fourth deposition steps are carried out for the same length of time and the deposition time for said third and fourth deposition steps are about 5/8 of the deposition time of said first and second deposition steps to provide for uniformity of thickness in material deposited during said first, second, third, and fourth deposition steps.

Claim 32

The process of claim 19 wherein the deposition time of said fifth deposition step is from about 1/8 to about 3/8 of the deposition time of said first and second deposition steps to provide for uniformity of thickness in material deposited during said five deposition steps.

Claim 33

The process of claim 19 wherein the deposition time of said fifth deposition step is about 1/4 of the deposition time of said first and second deposition steps to provide for uniformity of thickness in material deposited during said five deposition steps.

Claim 34

A multiple step process for sputter depositing a titanium layer of uniform thickness onto bottom and sidewall surfaces of a high aspect ratio opening formed through an insulating layer of an integrated circuit structure on a semiconductor substrate mounted on a support pedestal in a sputter deposition chamber having a sputtering target and an RF coil therein for coupling RF energy to a plasma maintained between the target and the support pedestal which comprises: a) in a first deposition step, sputter depositing titanium from said target onto at least the bottom surface of said high aspect ratio opening for a period of from about 10 to about 15 seconds while: i) maintaining said chamber at a high pressure of at least 35 millitorr; ii) providing thigh power RF energy of at least about 4 kilowatts (kw) to said coil in said deposition chamber; iii) applying a high power RF bias of at least about 400 watts to said pedestal supporting said substrate being deposited upon; and iv) applying a low power DC bias of not greater than 3 kw to said sputtering target; b) then, in a second deposition step, carried out for the same period of time as in said first deposition step, reducing said high power RF bias on said pedestal to a lower power by ramping said RF bias down to a level of zero at the end of said second deposition step, while maintaining said high pressure in said chamber and while maintaining said low power DC bias on said target and said high power RF energy to said coil, to thereby deposit titanium on at least a lowest quartile of said sidewall surface; c) then, in a third deposition step, carried out for a period of time of from about 1/2 to about 3/4 of the deposition time of said first and second deposition steps, applying no RF bias to said pedestal and reducing said pressure in said sputtering chamber to a medium pressure of from 10 millitorr to below 35 millitorr, while maintaining said low power DC bias on said target and said high RF power to said coil, to thereby deposit titanium on at least a second quartile of said sidewall surface; d) then, in a fourth deposition step, carried out for a period of time of from about 1/2 to about 3/4 of the deposition time of said first and second deposition steps, reducing said high power RF energy to said coil to low power RF energy of not greater than about 3 kw, while maintaining said pressure at said medium level and said DC bias on said target at a low state, with no RF bias applied to said pedestal to thereby deposit titanium on at least a third quartile of said sidewall surface; and e) then, in a fifth deposition step, carried out for a period of time of from about 1/8 to about 3/8 of the deposition time of said first and second deposition steps, lowering said chamber pressure further to a low pressure state of below 10 millitorr and applying a high power DC bias of greater than 3 kw to said target, while maintaining said RF energy to said coil at said low power level and no RF bias applied to said pedestal, to thereby deposit titanium on at least a fourth quartile of said sidewall surface; whereby a uniform thickness of titanium is sputtered onto substantially all of said bottom and sidewall surfaces of said high aspect ratio opening in said integrated circuit structure.

Claim 35

A multiple step process for sputter depositing a titanium layer of uniform thickness onto bottom and sidewall surfaces of a high aspect ratio opening formed through an insulating layer of an integrated circuit structure on a semiconductor substrate mounted on a support pedestal in a sputter deposition chamber having a sputtering target and an RF coil therein for coupling RF energy to a plasma maintained between the target and the support pedestal which comprises: a) in a first deposition step, sputter depositing titanium from said target onto at least the bottom surface of said high aspect ratio opening for a period of from about 10 to about 15 seconds while: i) maintaining said chamber at a high pressure of at least 35 millitorr; ii) providing thigh power RF energy of at least about 4 kilowatts (kw) to said coil in said deposition chamber; iii) applying a high power RF bias of at least about 400 watts to said pedestal supporting said substrate being deposited upon; and iv) applying a low power DC bias of not greater than 3 kw to said sputtering target; b) then, in a second deposition step, carried out for the same period of time as in said first deposition step, reducing said high power RF bias on said pedestal to a lower power by ramping said RF bias down to a level of zero at the end of said second deposition step, while maintaining said high pressure in said chamber and while maintaining said low power DC bias on said target and said high power RF energy to said coil, to thereby deposit titanium on at least a lowest quartile of said sidewall surface; c) then, in a third deposition step, carried out for a period of time of from about 1/2 to about 3/4 of the deposition time of said first and second deposition steps, applying no RF bias to said pedestal and reducing said pressure in said sputtering chamber to a medium pressure of from 10 millitorr to below 35 millitorr, while maintaining said low power DC bias on said target and said high RF power to said coil, to thereby deposit titanium on at least a second quartile of said sidewall surface; d) then, in a fourth deposition step, carried out for a period of time of from about 1/2 to about 3/4 of the deposition time of said first and second deposition steps, reducing said high power RF energy to said coil to low power RF energy of not greater than about 3 kw, while maintaining said pressure at said medium level and said DC bias on said target at a low state, with no RF bias applied to said pedestal to thereby deposit titanium on at least a third quartile of said sidewall surface; and e) then, in a fifth deposition step, carried out for a period of time of from about 1/8 to about 3/8 of the deposition time of said first and second deposition steps, lowering said chamber pressure further to a low pressure state of below 10 millitorr and applying a high power DC bias of greater than 3 kw to said target, while maintaining said RF energy to said coil at said low power level and no RF bias applied to said pedestal, to thereby deposit titanium on at least a fourth quartile of said sidewall surface; whereby a uniform thickness of titanium is sputtered onto substantially all of said bottom and sidewall surfaces of said high aspect ratio opening in said integrated circuit structure.

Claim 36

A multiple step process for sputter depositing a material of uniform thickness over a stepped surface of an integrated circuit structure on a semiconductor substrate on a support pedestal in a sputter deposition chamber having a sputtering target and at least one energy source to provide RF energy to a plasma maintained between the target and the support pedestal which comprises: a) in a first deposition step, sputter depositing material from said target onto at least a lowest region of said stepped surface while: i) maintaining said chamber at a high pressure; ii) providing a high power energy to said plasma in said deposition chamber; iii) applying a high power RF bias to said pedestal supporting said substrate being deposited upon; and iv) applying a low power DC bias to said sputtering target; b) then, in a second deposition step, reducing said high power RF bias on said pedestal to a lower power while continuing to deposit on said stepped surface, to thereby deposit at least on a higher region of said stepped surface; c) then, in a third deposition step, applying no RF bias to said pedestal and reducing said pressure in said sputtering chamber to a medium pressure, while continuing,to deposit on said stepped surface, to thereby deposit material on at least a second higher region of said stepped surface; d) then, in a fourth deposition step, reducing said high power energy to said plasma to low power RF energy while continuing to deposit on said stepped surface, to thereby deposit material on at least a third higher region of said stepped surface; and e) then, in a fifth deposition step, lowering said pressure in said chamber further to a low pressure state and applying a high power DC bias to said target, while continuing to deposit material on said stepped surface, to thereby deposit material on at least a highest region of said stepped surface; whereby a uniform thickness of material is sputtered onto said stepped surface.

Claim 37

A multiple step process for sputter depositing a material of uniform thickness over a stepped surface of an integrated circuit structure on a semiconductor substrate on a support pedestal in a sputter deposition chamber having a sputtering target and at least one energy source to provide RF energy to a plasma maintained between the target and the support pedestal which comprises: a) in a first deposition step, sputter depositing material from said target onto at least a lowest region of said stepped surface while: i) maintaining said chamber at a high pressure; ii) providing a high power energy to said plasma in said deposition chamber; iii) applying a high power RF bias to said pedestal supporting said substrate being deposited upon; and iv) applying a low power DC bias to said sputtering target; b) then, in a second deposition step, reducing said high power RF bias on said pedestal to a lower power while continuing to deposit on said stepped surface, to thereby deposit at least on a higher region of said stepped surface; c) then, in a third deposition step, applying no RF bias to said pedestal and reducing said pressure in said sputtering chamber to a medium pressure, while continuing,to deposit on said stepped surface, to thereby deposit material on at least a second higher region of said stepped surface; d) then, in a fourth deposition step, reducing said high power energy to said plasma to low power RF energy while continuing to deposit on said stepped surface, to thereby deposit material on at least a third higher region of said stepped surface; and e) then, in a fifth deposition step, lowering said pressure in said chamber further to a low pressure state and applying a high power DC bias to said target, while continuing to deposit material on said stepped surface, to thereby deposit material on at least a highest region of said stepped surface; whereby a uniform thickness of material is sputtered onto said stepped surface.