Patent US6080206A successfully refreshed from Google Patents.
US6080206A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of laying out interconnections
Assignee: Lapis Semiconductor Co Ltd
•
Filing: 1997-10-08
•
Granted: 2000-06-27
•
Expires: 2017-10-08
Abstract
Abstract To implement a method of laying out interconnections, which is capable of reducing a skew value of a predetermined signal and a delay in predetermined signal to the utmost, a region intended for a wiring layout employed in a CAD system is divided into a plurality of subregions and wiring regions dedicated to the predetermined signal in the respective subregions are set. The number of driver's stages in the respective subregions is set and the region is enlarged with the adjacent subregions identical in number of driver's stages as virtual subregions. Thus, the layout of wiring between the subregions is set.
Inventors
- 👤 Hirofumi Tadokoro
- 👤 Kenji Arai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:16
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/394; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
196 words
A method of laying out interconnections employed in an LSI logic circuit having a pluralitu of logic elements within a preset regiion of an LSI chip, the plurality of logic elements being respectively activated in synchronism with at least one predetermined signal through one or more drive elements, said method comprising: dividing the region into a plurality of subregions; setting, within the individual subregions, the number of drive elements to be interposed between an input position of the signal to the respective subregions and a transfer position of the signal to the logic elements within the region; setting drive elements, for sypplying the predetermined signal between the subregions, by grouping the subregions based on the number of driving elements in the respective subregions wherein said drive elements are set between subregions with the same number of driving elements or between subregions with the closest number of driving elements; wiring between the drive elements, which are operable to supply the at least one predetermined signal, using predetermined wiring regions; and setting wiring between the drive elements set in the subregions using the layout of the respective drive elements in the individual subregions and the set wiring regions.
Claim 2
Independent Claim
196 words
A method of laying out interconnections employed in an LSI logic circuit having a pluralitu of logic elements within a preset regiion of an LSI chip, the plurality of logic elements being respectively activated in synchronism with at least one predetermined signal through one or more drive elements, said method comprising: dividing the region into a plurality of subregions; setting, within the individual subregions, the number of drive elements to be interposed between an input position of the signal to the respective subregions and a transfer position of the signal to the logic elements within the region; setting drive elements, for sypplying the predetermined signal between the subregions, by grouping the subregions based on the number of driving elements in the respective subregions wherein said drive elements are set between subregions with the same number of driving elements or between subregions with the closest number of driving elements; wiring between the drive elements, which are operable to supply the at least one predetermined signal, using predetermined wiring regions; and setting wiring between the drive elements set in the subregions using the layout of the respective drive elements in the individual subregions and the set wiring regions.
Claim 3
Dependent Claim
31 words
A method according to claim 1, wherein the layout of the drive elements in the individual subregions and the wiring between the drive elements are conducted using an H-type clock tree.
Claim 4
Dependent Claim
49 words
A method according to claim 2, further including: configuring the H-type clock tree within a substantially square region in which the region is dividable into 2 n in the vertical or horizontal direction; and selecting only a divided region including main drive elements of the configured H-type clock tree.
Claim 5
Dependent Claim
51 words
A method according to claim 1, further including: aligning a region for a reference potential supply line with the wiring regions used to transfer the signal and placing the region for the reference potential supply line in a wiring layer different from a wiring layer for laying out the wiring regions.
Claim 6
Dependent Claim
31 words
A method according to claim 4, wherein the layout of the drive elements in the individual subregions and the wiring between the drive elements are conducted using an H-type clock tree.
Claim 7
Dependent Claim
49 words
A method according to claim 5, further including: configuring the H-type clock tree within a substantially square region in which the region is dividable into 2 n in the vertical or horizontal direction; and selecting only a divided region including main drive elements of said configured H-type clock tree.
Claim 8
Dependent Claim
47 words
A method according to claim 1, further including: setting other signal interconnections wired in the neighborhood of the wiring regions so as to be spaced by a predetermined interval from the wiring regions after the wiring regions used for the transfer of the signal have been set.
Claim 9
Dependent Claim
31 words
A method according to claim 7, wherein the layout of the drive elements in the individual subregions and the wiring between the drive elements are conducted using an H-type clock tree.
Claim 10
Dependent Claim
49 words
A method according to claim 8, further including: configuring the H-type clock tree within a substantially square region in which the region is dividable into 2 n in the vertical or horizontal direction; and selecting only a divided region including main drive elements of said configured H-type clock tree.
Claim 11
Dependent Claim
27 words
A method according to claim 1, further including: setting wiring regions used for the transfer of the signal within the region for setting said predetermined wiring regions.
References Cited (Backward Citations)
US5880971A
Cited
US5557779A
Cited
US5513124A
Cited
US5648913A
Cited
US5648911A
Cited
US5917729A
Cited
US5838581A
Cited
US5715408A
Cited
US6006023A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-27 | 2003-12-27 | 2004-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-27 | 2007-12-27 | 2008-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-27 | 2011-12-27 | 2012-06-27 | $7700.00 | Window Closed / Lapsed |