Process for making merged integrated circuits having salicide FETS and embedded DRAM circuits

Claim 1

A method for fabricating a merged integrated circuit having salicide field effect transistors (FETs) integrated with dynamic random access memory (DRAM) comprising the steps of: providing a semiconductor substrate having a logic region and a memory region having device areas, said device areas surrounded and electrically isolated from each other by field oxide areas; forming a first gate oxide on said device areas; depositing an undoped first polysilicon layer; depositing a first insulating layer on said first polysilicon layer; removing said first insulating layer and said first polysilicon layer over said memory region; forming a second gate oxide on said device areas in said memory region; depositing a doped second polysilicon layer and a refractory metal silicide layer to form a first polycide layer; depositing a hard-mask layer; patterning by masking and etching said hard-mask layer and first polycide layer to form gate electrodes in said device areas of said memory region, while protecting said logic region from etching; forming first source/drain areas adjacent to said gate electrodes in said memory region; forming insulating sidewall spacers on said gate electrodes in said memory region; forming a blanket conformal liner layer; depositing a second insulating layer to form an interpolysilicon oxide-1; chemically-mechanically polishing back said second insulating layer to said hard-mask layer over said logic region, and forming a planar second insulating layer over said memory region; removing said hard-mask layer, said first polycide layer, and said first insulating layer over said logic region, while said second insulating layer protects said memory region; patterning said undoped first polysilicon layer to form gate electrodes in said device areas of said logic region; forming lightly doped source/drain areas adjacent to said gate electrodes in said logic region; forming insulating sidewall spacers on said gate electrodes in said logic region; forming second source/drain areas by ion implantation adjacent to said sidewall spacers on said gate electrodes in said logic region, and concurrently doping said undoped polysilicon gate electrodes; forming a conformal metal layer and annealing to selectively form a metal silicide on said second source/drain areas and said polysilicon gate electrodes, and etching to remove said metal that is unreacted on said sidewall spacers and elsewhere on said substrate, thereby forming said salicide FETs; depositing a blanket etch-stop layer; depositing a third insulating layer and polishing back to said second insulating layer over said memory region; etching first contact openings in said second insulating layer and filling with a doped third polysilicon layer to form bit-line polysilicon plugs and capacitor node polysilicon plugs self-aligned to said gate electrodes in said memory region; depositing a fourth insulating layer and etching second contact openings to said bit-line polysilicon plugs; depositing a second polycide layer and patterning to form bit lines; depositing a fifth insulating layer to form an interpolysilicon oxide-2 layer, and etching third contact openings and filling with a doped polysilicon to form electrical contacts to said capacitor node polysilicon plugs; forming stacked capacitors over said electrical contacts, and depositing and planarizing a sixth insulating layer on said stacked capacitors; etching fourth contact openings to said first polycide layer in said memory region and to said metal silicide on said second source/drain areas in said logic region and filling with an electrically conducting material to form electrical contacts; depositing and patterning a low-resistivity metal layer to form first metal interconnections, and depositing an interlevel dielectric layer and etching fifth contact openings for the next level of metal interconnections, and repeating said metal deposition and patterning, and said interlevel dielectric layer deposition for each level necessary to complete said merged integrated circuit.

Claim 2

A method for fabricating a merged integrated circuit having salicide field effect transistors (FETs) integrated with dynamic random access memory (DRAM) comprising the steps of: providing a semiconductor substrate having a logic region and a memory region having device areas, said device areas surrounded and electrically isolated from each other by field oxide areas; forming a first gate oxide on said device areas; depositing an undoped first polysilicon layer; depositing a first insulating layer on said first polysilicon layer; removing said first insulating layer and said first polysilicon layer over said memory region; forming a second gate oxide on said device areas in said memory region; depositing a doped second polysilicon layer and a refractory metal silicide layer to form a first polycide layer; depositing a hard-mask layer; patterning by masking and etching said hard-mask layer and first polycide layer to form gate electrodes in said device areas of said memory region, while protecting said logic region from etching; forming first source/drain areas adjacent to said gate electrodes in said memory region; forming insulating sidewall spacers on said gate electrodes in said memory region; forming a blanket conformal liner layer; depositing a second insulating layer to form an interpolysilicon oxide-1; chemically-mechanically polishing back said second insulating layer to said hard-mask layer over said logic region, and forming a planar second insulating layer over said memory region; removing said hard-mask layer, said first polycide layer, and said first insulating layer over said logic region, while said second insulating layer protects said memory region; patterning said undoped first polysilicon layer to form gate electrodes in said device areas of said logic region; forming lightly doped source/drain areas adjacent to said gate electrodes in said logic region; forming insulating sidewall spacers on said gate electrodes in said logic region; forming second source/drain areas by ion implantation adjacent to said sidewall spacers on said gate electrodes in said logic region, and concurrently doping said undoped polysilicon gate electrodes; forming a conformal metal layer and annealing to selectively form a metal silicide on said second source/drain areas and said polysilicon gate electrodes, and etching to remove said metal that is unreacted on said sidewall spacers and elsewhere on said substrate, thereby forming said salicide FETs; depositing a blanket etch-stop layer; depositing a third insulating layer and polishing back to said second insulating layer over said memory region; etching first contact openings in said second insulating layer and filling with a doped third polysilicon layer to form bit-line polysilicon plugs and capacitor node polysilicon plugs self-aligned to said gate electrodes in said memory region; depositing a fourth insulating layer and etching second contact openings to said bit-line polysilicon plugs; depositing a second polycide layer and patterning to form bit lines; depositing a fifth insulating layer to form an interpolysilicon oxide-2 layer, and etching third contact openings and filling with a doped polysilicon to form electrical contacts to said capacitor node polysilicon plugs; forming stacked capacitors over said electrical contacts, and depositing and planarizing a sixth insulating layer on said stacked capacitors; etching fourth contact openings to said first polycide layer in said memory region and to said metal silicide on said second source/drain areas in said logic region and filling with an electrically conducting material to form electrical contacts; depositing and patterning a low-resistivity metal layer to form first metal interconnections, and depositing an interlevel dielectric layer and etching fifth contact openings for the next level of metal interconnections, and repeating said metal deposition and patterning, and said interlevel dielectric layer deposition for each level necessary to complete said merged integrated circuit.

Claim 12

A method for fabricating a merged integrated circuit having salicide field effect transistors (FETs) integrated with dynamic random access memory (DRAM) comprising the steps of: providing a semiconductor substrate having a logic region and a memory region having device areas, said device areas surrounded and electrically isolated from each other by field oxide areas; forming a first gate oxide on said device areas; depositing an undoped first polysilicon layer; depositing a first insulating layer on said first polysilicon layer; removing said first insulating layer and said first polysilicon layer over said memory region; forming a second gate oxide on said device areas in said memory region; depositing a doped second polysilicon layer and a tungsten metal silicide layer to form a first polycide layer; depositing a silicon nitride hard-mask layer; patterning by masking and etching said hard-mask layer and said first polycide layer to form gate electrodes in said device areas of said memory region, while protecting said logic region from etching; forming first source/drain areas adjacent to said gate electrodes in said memory region; forming insulating sidewall spacers on said gate electrodes in said memory region; forming a blanket conformal liner layer; depositing a second insulating layer to form an interpolysilicon oxide-1; chemically-mechanically polishing back said second insulating layer to said hard-mask layer over said logic region, and forming a planar second insulating layer over said memory region; removing said hard-mask layer, said first polycide layer, and said first insulating layer over said logic region, while said second insulating layer protects said memory region; patterning said undoped first polysilicon layer to form gate electrodes in said device areas of said logic region; forming lightly doped source/drain areas adjacent to said gate electrodes in said logic region; forming insulating sidewall spacers on said gate electrodes in said logic region; forming second source/drain areas by ion implantation adjacent to said sidewall spacers on said gate electrodes in said logic region, and concurrently doping said undoped polysilicon gate electrodes; depositing a conformal titanium metal layer and annealing to selectively form a titanium silicide on said second source/drain areas and on said polysilicon gate electrodes, and etching to remove said titanium metal that is unreacted on said sidewall spacers and elsewhere on said substrate, thereby forming said salicide FETs; depositing a blanket etch-stop layer; depositing a third insulating layer and polishing back to said second insulating layer over said memory region; etching first contact openings in said second insulating layer and filling with a doped polysilicon layer to form bit-line polysilicon plugs and capacitor node polysilicon plugs self-aligned to said gate electrodes in said memory region; depositing a fourth insulating layer and etching second contact openings to said bit-line polysilicon plugs; depositing a second polycide layer and patterning to form bit lines; depositing a fifth insulating layer to form an interpolysilicon oxide-2 layer, and etching third contact openings and filling with a doped polysilicon to form electrical contacts to said capacitor node polysilicon plugs; forming stacked capacitors over said electrical contacts, and depositing and planarizing a sixth insulating layer on said stacked capacitors; etching fourth contact openings to said first polycide layer in said memory region and to said metal silicide on said second source/drain areas in said logic region and filling with metal to form metal contacts; depositing and patterning a metal layer to form first metal interconnections, and depositing an interlevel dielectric layer and etching fifth contact openings for the next level of metal interconnections, and repeating said metal deposition and said interlevel dielectric layer deposition for each level necessary to complete said merged integrated circuit.

Claim 13

A method for fabricating a merged integrated circuit having salicide field effect transistors (FETs) integrated with dynamic random access memory (DRAM) comprising the steps of: providing a semiconductor substrate having a logic region and a memory region having device areas, said device areas surrounded and electrically isolated from each other by field oxide areas; forming a first gate oxide on said device areas; depositing an undoped first polysilicon layer; depositing a first insulating layer on said first polysilicon layer; removing said first insulating layer and said first polysilicon layer over said memory region; forming a second gate oxide on said device areas in said memory region; depositing a doped second polysilicon layer and a tungsten metal silicide layer to form a first polycide layer; depositing a silicon nitride hard-mask layer; patterning by masking and etching said hard-mask layer and said first polycide layer to form gate electrodes in said device areas of said memory region, while protecting said logic region from etching; forming first source/drain areas adjacent to said gate electrodes in said memory region; forming insulating sidewall spacers on said gate electrodes in said memory region; forming a blanket conformal liner layer; depositing a second insulating layer to form an interpolysilicon oxide-1; chemically-mechanically polishing back said second insulating layer to said hard-mask layer over said logic region, and forming a planar second insulating layer over said memory region; removing said hard-mask layer, said first polycide layer, and said first insulating layer over said logic region, while said second insulating layer protects said memory region; patterning said undoped first polysilicon layer to form gate electrodes in said device areas of said logic region; forming lightly doped source/drain areas adjacent to said gate electrodes in said logic region; forming insulating sidewall spacers on said gate electrodes in said logic region; forming second source/drain areas by ion implantation adjacent to said sidewall spacers on said gate electrodes in said logic region, and concurrently doping said undoped polysilicon gate electrodes; depositing a conformal titanium metal layer and annealing to selectively form a titanium silicide on said second source/drain areas and on said polysilicon gate electrodes, and etching to remove said titanium metal that is unreacted on said sidewall spacers and elsewhere on said substrate, thereby forming said salicide FETs; depositing a blanket etch-stop layer; depositing a third insulating layer and polishing back to said second insulating layer over said memory region; etching first contact openings in said second insulating layer and filling with a doped polysilicon layer to form bit-line polysilicon plugs and capacitor node polysilicon plugs self-aligned to said gate electrodes in said memory region; depositing a fourth insulating layer and etching second contact openings to said bit-line polysilicon plugs; depositing a second polycide layer and patterning to form bit lines; depositing a fifth insulating layer to form an interpolysilicon oxide-2 layer, and etching third contact openings and filling with a doped polysilicon to form electrical contacts to said capacitor node polysilicon plugs; forming stacked capacitors over said electrical contacts, and depositing and planarizing a sixth insulating layer on said stacked capacitors; etching fourth contact openings to said first polycide layer in said memory region and to said metal silicide on said second source/drain areas in said logic region and filling with metal to form metal contacts; depositing and patterning a metal layer to form first metal interconnections, and depositing an interlevel dielectric layer and etching fifth contact openings for the next level of metal interconnections, and repeating said metal deposition and said interlevel dielectric layer deposition for each level necessary to complete said merged integrated circuit.