US6072219A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Substrate-triggering electrostatic discharge protection circuit for deep-submicron integrated circuits
Assignee: United Microelectronics Corp
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Filing: 1998-03-03
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Granted: 2000-06-06
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Expires: 2018-03-03
Abstract
Abstract A substrate-triggering ESD protection circuit is provided for use on a deep-submicron integrated circuit for ESD protection of the integrated circuit. The ESD protection circuit is incorporated between an input end and the internal circuit of the integrated circuit formed on a substrate. The ESD protection circuit utilizes a featured substrate-triggering operation to trigger the ESD-protection transistors formed in N-wells of the substrate into conducting state so as to bypass the ESD current to the ground. The ESD protection circuit allows a simplified semiconductor structure to fabricate, while nonetheless providing an increased level of ESD protection capability for the deep-submicron integrated circuit.
Inventors
- 👤 Ming-Dou Ker
- 👤 Tung-Yang Chen
- 👤 Chung-Yu Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 17:17
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/8311
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
187 words
An electrostatic discharge (ESD) protection circuit incorporated between an input pad and an internal circuit of an integrated circuit formed on a substrate, said ESD protection circuit comprising: an input stage connected between the input pad and the internal circuit of the integrated circuit; an NMOS transistor having a drain connected to the input pad, a gate connected to the ground, and a source connected to a common node; a resistor connected between the common node and the ground; and an field oxide device (FOD) having a parasitic lateral bipolar junction transistor (LBJT) formed therein, and said FOD having a drain connected to the input pad and a source connected to the ground; wherein the substrate of said FOD and the source and substrate of said NMOS transistor are connected together to the common node; wherein said parasitic LBJT has a collector formed from the drain of said FOD and an emitter formed from the source of said FOD, and a base formed from the substrate of said FOD; and wherein a breakdown voltage of sad NMOS transistor is lower than a breakdown voltage of said FOD.
Claim 2
Dependent Claim
187 words
An electrostatic discharge (ESD) protection circuit incorporated between an input pad and an internal circuit of an integrated circuit formed on a substrate, said ESD protection circuit comprising: an input stage connected between the input pad and the internal circuit of the integrated circuit; an NMOS transistor having a drain connected to the input pad, a gate connected to the ground, and a source connected to a common node; a resistor connected between the common node and the ground; and an field oxide device (FOD) having a parasitic lateral bipolar junction transistor (LBJT) formed therein, and said FOD having a drain connected to the input pad and a source connected to the ground; wherein the substrate of said FOD and the source and substrate of said NMOS transistor are connected together to the common node; wherein said parasitic LBJT has a collector formed from the drain of said FOD and an emitter formed from the source of said FOD, and a base formed from the substrate of said FOD; and wherein a breakdown voltage of sad NMOS transistor is lower than a breakdown voltage of said FOD.
Claim 3
Dependent Claim
15 words
The ESD protection circuit of claim 1, wherein said input stage is a CMOS circuit.
Claim 4
Dependent Claim
17 words
The ESD protection circuit of claim 1, wherein said NMOS transistor is formed with a short channel.
Claim 5
Dependent Claim
14 words
The ESD protection circuit of claim 1, wherein said substrate is a P-type substrate.
Claim 6
Dependent Claim
221 words
An electrostatic discharge (ESD) protection circuit incorporated between an input pad and an internal circuit of an integrated circuit formed on a substrate, said ESD protection circuit compromising: an input stage connected between the input pad and the internal circuit of the integrated circuit; a first NMOS transistor having a drain connected to the input pad, a gate connected to the ground, and a source connected to a common node, and the substrate of said first NMOS transistor being connected to the common node; a resistor connected between the common node and the ground; and a second NMOS transistor having a parasitic lateral bipolar junction transistor (LBJT) formed therein, and said second NMOS transistor having a drain connected to the input pad, a source connected to the ground, and a gate connected to the ground; wherein the substrate of said second NMOS transistor and the source and substrate of said first NMOS transistor are connected together to the common node; wherein said parasitic LBJT has a collector formed from the drain of said second NMOS transistor and an emitter formed from the source of said second NMOS transistor, and a base formed from the substrate of said second NMOS transistor; and wherein a breakdown voltage of said first NMOS transistor is lower than a breakdown voltage of said second NMOS transistor.
Claim 7
Dependent Claim
221 words
An electrostatic discharge (ESD) protection circuit incorporated between an input pad and an internal circuit of an integrated circuit formed on a substrate, said ESD protection circuit compromising: an input stage connected between the input pad and the internal circuit of the integrated circuit; a first NMOS transistor having a drain connected to the input pad, a gate connected to the ground, and a source connected to a common node, and the substrate of said first NMOS transistor being connected to the common node; a resistor connected between the common node and the ground; and a second NMOS transistor having a parasitic lateral bipolar junction transistor (LBJT) formed therein, and said second NMOS transistor having a drain connected to the input pad, a source connected to the ground, and a gate connected to the ground; wherein the substrate of said second NMOS transistor and the source and substrate of said first NMOS transistor are connected together to the common node; wherein said parasitic LBJT has a collector formed from the drain of said second NMOS transistor and an emitter formed from the source of said second NMOS transistor, and a base formed from the substrate of said second NMOS transistor; and wherein a breakdown voltage of said first NMOS transistor is lower than a breakdown voltage of said second NMOS transistor.
Claim 8
Dependent Claim
18 words
The ESD protection circuit of claim 5, wherein said first NMOS transistor is formed with a short channel.
Claim 9
Dependent Claim
18 words
The ESD protection circuit of claim 5, wherein said second NMOS transistor is formed with a long channel.
Claim 10
Dependent Claim
14 words
The ESD protection circuit of claim 5, wherein said substrate is a P-type substrate.
Claim 11
Dependent Claim
249 words
An electrostatic discharge (ESD) protection circuit incorporated between an input pad and an internal circuit of an integrated circuit formed on a substrate, said ESD protection circuit compromising; an input stage connected between the input and the internal circuit of the integrated circuit; a first NMOS transistor having a channel of a first semiconductor type, said first NMOS transistor further having a drain connected to the input pad, a gate connected to a bias point, and a source connected to a common node, and the substrate of said first NMOS transistor being connected to the common node; a resistor connected between the common node and the bias point; and a second NMOS transistor having a channel of the first semiconductor type, said second NMOS transistor further having a parasitic lateral bipolar junction transistor (LBJT) formed therein, and said second NMOS transistor having a drain connected to the input pad, a source connected to the bias point, and a gate connected to the bias point; wherein the substrate of said second NMOS transistor and the source and substrate of said first NMOS transistor are connected together to the common node; wherein said parasitic LBJT has a collector formed from the drain of said second NMOS transistor and an emitter formed the source of said second NMOS transistor, and a base formed from the substrate of said second NMOS transistor; and wherein a breakdown voltage of said first NMOS transistor is lower than a breakdown voltage of said second NMOS transistor.
Claim 12
Dependent Claim
249 words
An electrostatic discharge (ESD) protection circuit incorporated between an input pad and an internal circuit of an integrated circuit formed on a substrate, said ESD protection circuit compromising; an input stage connected between the input and the internal circuit of the integrated circuit; a first NMOS transistor having a channel of a first semiconductor type, said first NMOS transistor further having a drain connected to the input pad, a gate connected to a bias point, and a source connected to a common node, and the substrate of said first NMOS transistor being connected to the common node; a resistor connected between the common node and the bias point; and a second NMOS transistor having a channel of the first semiconductor type, said second NMOS transistor further having a parasitic lateral bipolar junction transistor (LBJT) formed therein, and said second NMOS transistor having a drain connected to the input pad, a source connected to the bias point, and a gate connected to the bias point; wherein the substrate of said second NMOS transistor and the source and substrate of said first NMOS transistor are connected together to the common node; wherein said parasitic LBJT has a collector formed from the drain of said second NMOS transistor and an emitter formed the source of said second NMOS transistor, and a base formed from the substrate of said second NMOS transistor; and wherein a breakdown voltage of said first NMOS transistor is lower than a breakdown voltage of said second NMOS transistor.
Claim 13
Dependent Claim
19 words
The ESD protection circuit of claim 9, wherein said channel of the first semiconductor type is an N-type channel.
Claim 14
Dependent Claim
14 words
The ESD protection circuit of claim 10, wherein said substrate is a P-type substrate.
Claim 15
Dependent Claim
19 words
The ESD protection circuit of claim 9, wherein said channel of the first semiconductor type is a P-type channel.
Claim 16
Dependent Claim
14 words
The ESD protection circuit of claim 12, wherein said substrate is an N-type substrate.
Claim 17
Dependent Claim
18 words
The ESD protection circuit of claim 9, wherein said first NMOS transistor is formed with a short channel.
Claim 18
Dependent Claim
18 words
The ESD protection circuit of claim 9, wherein said second NMOS transistor is formed with a long channel.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2003-06-06 | 2003-12-06 | 2004-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-06 | 2007-12-06 | 2008-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-06 | 2011-12-06 | 2012-06-06 | $7700.00 | Window Closed / Lapsed |