Patent US3859764A successfully refreshed from Google Patents.
US5615073A
Expired / Lapsed
US
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Electrostatic discharge protection apparatus
Assignee: National Semiconductor Corp
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Filing: 1995-06-22
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Granted: 1997-03-25
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Expires: 2015-06-22
Abstract
Abstract A protection system for an integrated circuit includes a protection structure for the input terminals and output terminals that protects against ESD stress in bonding pad to V SS and bonding pad to V DD paths, both negative and positive paths. The protection system also includes a protection structure for protecting bonding pad to bonding pad electrical paths and a protection structure for V DD to V SS paths. Using all three protection structures in combination provides full protection against ESD events in all possible paths in an integrated circuit. A protection structure isolates an output buffer from the protection structure and encourages stress discharge through the protection structure rather than the output buffer. In addition, a set of design rules is set forth for the design and layout of the output buffer and protection structure including rules pertaining to transistor width, finger width, channel length, contact to gate spacing, and the like which significantly enhance ESD protection. In one embodiment, an electrostatic discharge (ESD) protection circuit connected to a pad of a semiconductor integrated circuit includes an NMOS transistor having a gate and a source/drain pathway connected between the pad and ground, a resistor connected between the NMOS transistor gate and ground, and a clamping transistor having a source/drain pathway connected between the NMOS transistor gate and ground and having a gate connected to the NMOS transistor gate. Supply taps are positioned at a distance removed from the NMOS transistor so that the substrate resistance at the NMOS transistor is elevated.
Inventors
- 👤 Rafael Fried
- 👤 Yaron Blecher
- 👤 Shimon Friedman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 08:25
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/60; H10D89/601; H10D89/811; H10D89/813; H10D89/815; H10D89/611
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
68 words
An electrostatic discharge (ESD) protection circuit connected to a pad of a semiconductor integrated circuit comprising: an NMOS transistor having a gate and a source/drain pathway coupled between the pad and ground; a resistor coupled between the NMOS transistor gate and ground; and a clamping transistor having a source/drain pathway coupled between the NMOS transistor gate and ground and having a gate coupled to the NMOS transistor gate.
Claim 2
Dependent Claim
68 words
An electrostatic discharge (ESD) protection circuit connected to a pad of a semiconductor integrated circuit comprising: an NMOS transistor having a gate and a source/drain pathway coupled between the pad and ground; a resistor coupled between the NMOS transistor gate and ground; and a clamping transistor having a source/drain pathway coupled between the NMOS transistor gate and ground and having a gate coupled to the NMOS transistor gate.
Claim 3
Dependent Claim
16 words
A circuit according to claim 1 further comprising: an elevated substrate resistance at the NMOS transistor.
Claim 4
Dependent Claim
30 words
A circuit according to claim 2 wherein: supply taps are positioned at a distance removed from the NMOS transistor so that the substrate resistance at the NMOS transistor is elevated.
Claim 5
Dependent Claim
19 words
A circuit according to claim 1 wherein: the pad is a bonding pad for connecting a VDD voltage source.
Claim 6
Dependent Claim
56 words
A circuit according to claim 1 wherein the NMOS transistor is a first NMOS transistor, the circuit further comprising: a second NMOS transistor having a gate and having a source/drain pathway coupled between a VDD supply voltage source and the pad; and a resistor coupled between the gate of the second NMOS transistor and the pad.
Claim 7
Dependent Claim
20 words
A circuit according to claim 5 further comprising: a diode coupled between the VDD supply voltage source and the pad.
Claim 8
Dependent Claim
13 words
A circuit according to claim 6 wherein the diode is a P+N- diode.
Claim 9
Dependent Claim
20 words
A circuit according to claim 1 further comprising: a diode coupled between the VDD supply voltage source and the pad.
Claim 10
Dependent Claim
13 words
A circuit according to claim 8 wherein the diode is a P+N- diode.
Claim 11
Dependent Claim
28 words
A circuit according to claim 1 wherein the pad is connected to a buffer, the circuit further comprising: a diffusion resistor coupled between the pad and the buffer.
Claim 12
Dependent Claim
16 words
A circuit according to claim 10 further comprising: a well tab positioned under the diffusion resistor.
Claim 13
Dependent Claim
72 words
An electrostatic discharge (ESD) protection circuit connected to a pad of a semiconductor integrated circuit comprising: a first NMOS transistor having a gate coupled to ground and a source/drain pathway coupled between the pad and ground; a second NMOS transistor having a gate and a source/drain pathway coupled between the VDD supply voltage source and the pad; and a resistor coupled between the gate of the second NMOS transistor and the pad.
Claim 14
Dependent Claim
72 words
An electrostatic discharge (ESD) protection circuit connected to a pad of a semiconductor integrated circuit comprising: a first NMOS transistor having a gate coupled to ground and a source/drain pathway coupled between the pad and ground; a second NMOS transistor having a gate and a source/drain pathway coupled between the VDD supply voltage source and the pad; and a resistor coupled between the gate of the second NMOS transistor and the pad.
Claim 15
Dependent Claim
20 words
A circuit according to claim 12 further comprising: a diode coupled between the VDD supply voltage source and the pad.
Claim 16
Dependent Claim
13 words
A circuit according to claim 13 wherein the diode is a P+N- diode.
Claim 17
Dependent Claim
28 words
A circuit according to claim 12 wherein the pad is connected to a buffer, the circuit further comprising: a diffusion resistor coupled between the pad and the buffer.
Claim 18
Dependent Claim
16 words
A circuit according to claim 14 further comprising: a well tab positioned under the diffusion resistor.
Claim 19
Dependent Claim
62 words
An electrostatic discharge (ESD) protection circuit connected between two pads of a semiconductor integrated circuit comprising: a field oxide transistor coupled between the two pads, the field oxide transistor including: a source diffusion; a drain diffusion; and an oxide layer between the drain and source diffusions; and an N-well formed under the source diffusion; and an N-well formed under the drain diffusion.
Claim 20
Dependent Claim
62 words
An electrostatic discharge (ESD) protection circuit connected between two pads of a semiconductor integrated circuit comprising: a field oxide transistor coupled between the two pads, the field oxide transistor including: a source diffusion; a drain diffusion; and an oxide layer between the drain and source diffusions; and an N-well formed under the source diffusion; and an N-well formed under the drain diffusion.
Claim 21
Dependent Claim
21 words
An electrostatic discharge (ESD) protection circuit according to claim 17 wherein the field oxide transistor is a gateless field oxide transistor.
Claim 22
Dependent Claim
145 words
An electrostatic discharge (ESD) protection system for protecting an integrated circuit having a plurality of transistors, a plurality of pads for connecting an input line, an output line, a VDD power supply line and a VSS ground reference line, the system comprising: a first protection structure coupled between a pad of the plurality of pads and a pad of the plurality of pads coupled to the V SS ground reference line and coupled between a pad of the plurality of pads and a pad of the plurality of pads coupled to the V DD power supply line for respectively protecting against ESD stress in pad to V SS and pad to V DD paths; and a second protection structure coupled between a first pad of the plurality of pads and a second pad of the plurality of pads for protecting pad to pad electrical paths.
Claim 23
Dependent Claim
145 words
An electrostatic discharge (ESD) protection system for protecting an integrated circuit having a plurality of transistors, a plurality of pads for connecting an input line, an output line, a VDD power supply line and a VSS ground reference line, the system comprising: a first protection structure coupled between a pad of the plurality of pads and a pad of the plurality of pads coupled to the V SS ground reference line and coupled between a pad of the plurality of pads and a pad of the plurality of pads coupled to the V DD power supply line for respectively protecting against ESD stress in pad to V SS and pad to V DD paths; and a second protection structure coupled between a first pad of the plurality of pads and a second pad of the plurality of pads for protecting pad to pad electrical paths.
Claim 24
Dependent Claim
60 words
A system according to claim 19, further comprising: a third protection structure coupled between a pad of the plurality of pads coupled to the V DD power supply line and a pad of the plurality of pads coupled to the V SS ground reference line for preventing the V DD potential from rising above the snap-back voltage of the transistors.
Claim 25
Dependent Claim
87 words
A system according to claim 20, wherein the third protection structure further comprises: a field oxide transistor coupled between the pad of the plurality of pads coupled to the V DD power supply line and the pad of the plurality of pads coupled to the V SS ground reference line, the field oxide transistor including: a source diffusion; a drain diffusion; and an oxide layer between the drain and source diffusions; and an N-well formed under the source diffusion; and an N-well formed under the drain diffusion.
Claim 26
Dependent Claim
112 words
A system according to claim 19, wherein the first protection structure further comprises: an NMOS transistor having a gate and a source/drain pathway coupled between a pad of the plurality of pads and the pad of the plurality of pads coupled to the V SS ground reference line; a resistor coupled between the NMOS transistor gate and the pad of the plurality of pads coupled to the V SS ground reference line; and a clamping transistor having a source/drain pathway coupled between the NMOS transistor gate and the pad of the plurality of pads coupled to the V SS ground reference line and having a gate coupled to the NMOS transistor gate.
Claim 27
Dependent Claim
72 words
A system according to claim 22, wherein the NMOS transistor is a first NMOS transistor, the first protection structure further comprising: a second NMOS transistor having a gate and having a source/drain pathway coupled between the pad coupled to the VDD supply voltage source and a pad of the plurality of pads; and a resistor coupled between the gate of the second NMOS transistor and the pad of the plurality of pads.
Claim 28
Dependent Claim
31 words
A system according to claim 23, wherein the first protection structure further comprises: a P+N- diode coupled between the VDD supply voltage source and a pad of the plurality of pads.
Claim 29
Dependent Claim
87 words
A system according to claim 19, wherein the second protection structure further comprises: a field oxide transistor coupled between the pad of the plurality of pads coupled to the V DD power supply line and the pad of the plurality of pads coupled to the V SS ground reference line, the field oxide transistor including: a source diffusion; a drain diffusion; and an oxide layer between the drain and source diffusions; and an N-well formed under the source diffusion; and an N-well formed under the drain diffusion.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-24 | 2000-09-23 | 2001-03-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-24 | 2004-09-23 | 2005-03-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-24 | 2008-09-23 | 2009-03-25 | $7700.00 | Window Closed / Lapsed |