Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
74 words
An NMOS ESD circuit, comprising: a thin oxide transistor, having its drain-to-source path connected between a signal terminal and a reference voltage supply and having a gate, and a high threshold transistor, having a threshold voltage greater than a preselected power supply voltage, having its drain connected to the gate of said first thin oxide transistor, having its source connected to said reference voltage supply, and having its gate connected to said signal terminal.
Claim 2
Dependent Claim
25 words
The ESD circuit of Claim 1, further comprising an N-well resistor connected between said reference voltage supply and said gate of said thin oxide transistor.
Claim 3
Dependent Claim
19 words
The ESD circuit of Claim 1 or Claim 2, wherein said high threshold transistor comprises a field oxide transistor.
Claim 4
Dependent Claim
19 words
The ESD circuit of any preceding claim, wherein said signal terminal is an output terminal of an output buffer.
Claim 5
Dependent Claim
16 words
The ESD circuit of any preceding claim, wherein said signal terminal is an input signal terminal.
Claim 6
Dependent Claim
16 words
The ESD circuit of any preceding claim, wherein said signal terminal is a voltage reference line.
Claim 7
Dependent Claim
16 words
The ESD circuit of any preceding claim for an integrated circuit formed in a semiconductor body.
Claim 8
Independent Claim
71 words
A method for ESD protection of an integrated circuit, comprising: capacitively coupling the voltage from an ESD event to the gate of an NMOS device, using said capacitively coupled voltage to turn-on said NMOS device, discharging said voltage from said ESD event to a reference voltage supply through said turned on NMOS device, and discharging said capacitively coupled voltage on said gate of said NMOS device to said reference voltage supply.
Claim 9
Independent Claim
69 words
A method for ESD protection, comprising: applying a capacitively coupled voltage from an ESD event to provide a first trigger, discharging the voltage of said ESD event to a reference voltage supply responsive to said first trigger, applying a portion of the voltage of said ESD event to provide a second trigger, and discharging said applied capacitively coupled voltage to said reference voltage supply responsive to said second trigger.