System and method of memory access in apparatus having plural processors and plural memories

Claim 2

A multi-processing system comprising: a plurality of n processors, each of said processors operable from an instruction stream provided from a memory source for controlling a process, said process relying on the movement of data to and from one or more addressable memories, each processor having a first data port and a second data port; a plurality of m memory sources, each memory source having a unique addressable space; a switch matrix having first links connected to said memories and second links connected to said first and second data ports of said processors, said switch matrix selectively connecting said first and second links whereby said first data port of each of said n processors may access any of said m memory sources and said second data port of each of said n processors may access only a predetermined corresponding subset of said m memory sources.

Claim 3

The multi-processing system set forth in claim 1 wherein said connection of said second data ports of each of said n processors to each of said predetermined unique subset of said m memory sources is via a split one of said second links of said switch matrix.

Claim 4

The multi-processing system set forth in claim 2 wherein said switch matrix includes crosspoints for interconnecting said first and second links and wherein said n processors, said m memory sources and said switch matrix, including said first and second links and said crosspoints are all constructed on a single integrated circuit, and wherein said first and second links and said crosspoints of said switch matrix are distributed across said single integrated circuit in spatial relationship with said n processors and said m memory sources.

Claim 5

The multi-processing system set forth in claim 1, wherein: said number of memory sources m is an integral multiple k of the number of processors n; said switch matrix includes crosspoints for interconnecting said first and second links; said n processors are disposed linearly; said m memory sources are disposed linearly opposite said n processors, a corresponding k of said memory sources disposed opposite each of said processors; and said switch matrix is disposed between said n processors and said m memory sources, said crosspoints connected to said second links of each of said n processors further connected to said first links of said corresponding k of said memory sources and disposed between said one of said n processors and said corresponding k of said memory sources.

Claim 6

The multi-processor system set forth in claim 1, wherein: said predetermined corresponding subset of said m memory sources accessible by said second data ports of each of said processors consists of said corresponding k of said memory sources.

Claim 7

The multi-processor system set forth in claim 1, further comprising: an external memory not directly connected to said switch matrix; a transfer processor connected to said switch matrix for access to said plurality of memory sources and to said external memory, said transfer processor controlling data transfer from a selected one of said m memory sources via said switch matrix to said external memory and data transfer form said external memory to a selected one of said m memory sources via said switch matrix.

Claim 10

The method set forth in claim 7 wherein said switch matrix contains a plurality of crosspoints and wherein said method includes the step of: operating said crosspoints on a cycle-by-cycle basis to effect said interconnecting of processors and memories.

Claim 11

The method set forth in claim 7 further including the step of: responding to provided addresses for controlling said crosspoints.

Claim 12

The method set forth in claim 7 wherein each said crosspoint includes a prioritization control system and wherein said method further includes the step of: sequencing simultaneous processor access attempts to the same memory.

Claim 13

The method set forth in claim 10 wherein said prioritization control system includes the step of sequential token passing.

Claim 14

The method set forth in claim 11 wherein said token passing step includes the step of: insuring lowest priority memory accessed to the processor which last successfully assessed the memory associated with said crosspoint.

Claim 15

The method set forth in claim 7, wherein the number of memory sources m is an integral multiple k of the number of processors n, and wherein: said step of selectively connecting via the switch matrix the second data port of each of said n processors to only a predetermined corresponding subset of said m memory sources consists of connecting the second data port of each of the n processors further connected to a selected one of k of said memory sources corresponding to the processor.

Claim 16

The method forth in claim 7 said multi-processing system further having an external memory not directly connected to said switch matrix, and a transfer processor connected to said switch matrix and said external memory, said method further comprising the steps of: transferring data from a selected one of said m memory sources via said switch matrix and said transfer processor to said external memory; and transferring data from said external memory to a selected one of said m memory sources via said switch matrix and said transfer processor.

Claim 17

An image processing system comprising: a master processor for controlling said image processing system, said master processor having a data port; a plurality of n processors, each of said processors operable from an instruction stream provided from a memory source for controlling a process, said process relying on the movement of data to and from one or more addressable memories, each processor having a first data port and a second data port; a plurality of m memory sources, each memory source having a unique addressable space; a switch matrix having first links connected to said memories and second links connected to said data port of said master processor and to said first and second data ports of said n processors, said switch matrix selectively connecting said first and second links whereby said data port of said master processor may access any of said m memory sources, selectively connecting said first and second links whereby said first data port of each of said n processors may access any of said m memory sources, and selectively connecting said first and second links whereby said second data port of each of said n processors may access only a predetermined corresponding subset of said m memory sources.

Claim 18

An image processing system comprising: a master processor for controlling said image processing system, said master processor having a data port; a plurality of n processors, each of said processors operable from an instruction stream provided from a memory source for controlling a process, said process relying on the movement of data to and from one or more addressable memories, each processor having a first data port and a second data port; a plurality of m memory sources, each memory source having a unique addressable space; a switch matrix having first links connected to said memories and second links connected to said data port of said master processor and to said first and second data ports of said n processors, said switch matrix selectively connecting said first and second links whereby said data port of said master processor may access any of said m memory sources, selectively connecting said first and second links whereby said first data port of each of said n processors may access any of said m memory sources, and selectively connecting said first and second links whereby said second data port of each of said n processors may access only a predetermined corresponding subset of said m memory sources.

Claim 19

The image processing system set forth in claim 15, further comprising: an external memory; and a transfer processor connected to said switch matrix and said external memory for transferring data between said external memory and said m memory sources via said switch matrix.