US5133073A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Processor array of N-dimensions which is physically reconfigurable into N-1
Assignee: WAVETRACER Inc A MA CORP
•
Filing: 1990-05-29
•
Granted: 1992-07-21
•
Expires: 2010-05-29
Abstract
Abstract A reconfigurable multi-dimensional processor array for processing multi-dimensionally structured data includes a plurality of processor cells arranged in N dimensions and having a plurality of N-1 dimensional processor subarrays. Each of the processor cells has 2N data signal ports operative for forming data signal paths for transmitting and receiving data to and from 2N adjacent processor cells or data communication devices. Each of the N-1 dimensional processor subarrays includes a selected group of processor cells coupled to fewer than 2N other processor cells or data communications devices. Each of the selected group of processor cells includes at least one uncoupled data signal port. An intermediary connection couples selected uncoupled data signal ports from at least a first N-1 dimensional processor subarray to selected uncoupled data signal ports from at least a second N-1 dimensional processor subarray, to form selected data signal paths between selected processor cells within the at least first and second N-1 dimensional processor subarrays.
Inventors
- 👤 James H. Jackson
- 👤 Ming-Chih Lee
- 👤 Mark R. LaForest
- 👤 Richard D. Fiorentino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 05:13
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17337; G06F15/17343; G06F15/76; G06F15/80; G06F15/8007; G06F15/803
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
155 words
A reconfigurable, multi-dimensional processor array, for processing multi-dimensionally structured data comprising: a plurality of processor cells arranged in N dimensions, N being at least 2, and having a plurality of N-1 dimensional processor subarrays; each of said plurality of processor cells including 2N data signal ports operative for forming 2N data signal paths, for transmitting and receiving data to and from up to 2N data communications devices; each of said plurality of N-1 dimensional processor subarrays including a selected group of processor cells having at least one unused data signal port; and a plurality of intermediary connections, forming data signal paths between unused data signal ports of a first selected group of processor cells from at least a first N-1 dimensional processor subarray, and unused data signal ports of a second selected group of processor cells from at least a second N-1 dimensional processor subarray, for providing a reconfigured processor array of fewer than N-dimensions.
Claim 2
Dependent Claim
155 words
A reconfigurable, multi-dimensional processor array, for processing multi-dimensionally structured data comprising: a plurality of processor cells arranged in N dimensions, N being at least 2, and having a plurality of N-1 dimensional processor subarrays; each of said plurality of processor cells including 2N data signal ports operative for forming 2N data signal paths, for transmitting and receiving data to and from up to 2N data communications devices; each of said plurality of N-1 dimensional processor subarrays including a selected group of processor cells having at least one unused data signal port; and a plurality of intermediary connections, forming data signal paths between unused data signal ports of a first selected group of processor cells from at least a first N-1 dimensional processor subarray, and unused data signal ports of a second selected group of processor cells from at least a second N-1 dimensional processor subarray, for providing a reconfigured processor array of fewer than N-dimensions.
Claim 3
Dependent Claim
14 words
The processor array of claim 1 wherein said data communication devices include processor cells.
Claim 4
Dependent Claim
25 words
The processor array of claim 1 wherein said data communication devices include input/output devices for transmitting and receiving data to and from the processor array.
Claim 5
Dependent Claim
25 words
The processor array of claim 1 wherein said first and second selected group of processor cells are coupled to fewer than 2N data communications devices.
Claim 6
Dependent Claim
15 words
The processor array of claim 1 wherein said multi-dimensional array is arranged in three dimensions.
Claim 7
Dependent Claim
11 words
The processor array of claim 5 wherein said subarrays are two-dimensional.
Claim 8
Dependent Claim
26 words
The processor array of claim 1 wherein data is transmitted and received among each of said plurality of processor cells in at least one predetermined direction.
Claim 9
Dependent Claim
25 words
The processor array of claim 7 wherein processor cells of said reconfigured processor array transmit and receive data in said at least one predetermined direction.
Claim 10
Dependent Claim
20 words
The processor array of claim 1 wherein said plurality of intermediary connections include selectively controllable and selectively activated intermediary connections.
Claim 11
Dependent Claim
116 words
A reconfigurable, multi-dimensional processor array, for processing multi-dimensionally structured data comprising: a plurality of processor cells arranged in N-dimensions, being at least 2,; each of said plurality of processor cells including 2N data signal ports operative for forming 2N data signal paths, for transmitting and receiving data to and from up to 2N data communications devices; said plurality of processor cells including a selected group of processor cells having at least one data signal port which is unused for data communications; and a plurality of intermediary connections, forming data signal paths between unused data signal ports of predetermined processor cells from said selected group of processor cells, for providing a processor array of fewer than N-dimensions.
Claim 12
Dependent Claim
116 words
A reconfigurable, multi-dimensional processor array, for processing multi-dimensionally structured data comprising: a plurality of processor cells arranged in N-dimensions, being at least 2,; each of said plurality of processor cells including 2N data signal ports operative for forming 2N data signal paths, for transmitting and receiving data to and from up to 2N data communications devices; said plurality of processor cells including a selected group of processor cells having at least one data signal port which is unused for data communications; and a plurality of intermediary connections, forming data signal paths between unused data signal ports of predetermined processor cells from said selected group of processor cells, for providing a processor array of fewer than N-dimensions.
Claim 13
Dependent Claim
163 words
A three dimensional processor array reconfigurable as a two-dimensional processor array for processing multi-dimensionally structured data comprising: a plurality of processor cells arranged in three dimensions and having a plurality of two-dimensional subarrays; each of said plurality of processor cells having six data signal ports operative for forming six data signal paths for transmitting and receiving data to and from up to six dimensionally adjacent processor cells; each of said plurality of two-dimensional subarrays including a selected group of processor cells having at least one unused data signal port; and a plurality of intermediary connections coupling unused data signal ports of a plurality of said selected group of processor cells from at least a first two-dimensional processor subarray, with a plurality of said selected group of processor cells from at least a second two-dimensional processor subarray, for forming data signal paths between said at least first and second two-dimensional processor subarrays, for reconfiguring said three dimensional processor array to a two-dimensional processor array.
Claim 14
Dependent Claim
163 words
A three dimensional processor array reconfigurable as a two-dimensional processor array for processing multi-dimensionally structured data comprising: a plurality of processor cells arranged in three dimensions and having a plurality of two-dimensional subarrays; each of said plurality of processor cells having six data signal ports operative for forming six data signal paths for transmitting and receiving data to and from up to six dimensionally adjacent processor cells; each of said plurality of two-dimensional subarrays including a selected group of processor cells having at least one unused data signal port; and a plurality of intermediary connections coupling unused data signal ports of a plurality of said selected group of processor cells from at least a first two-dimensional processor subarray, with a plurality of said selected group of processor cells from at least a second two-dimensional processor subarray, for forming data signal paths between said at least first and second two-dimensional processor subarrays, for reconfiguring said three dimensional processor array to a two-dimensional processor array.
References Cited (Backward Citations)
US3902160A
Cited
US3891836A
Cited
US3936885A
Cited
US4064392A
Cited
US3970993A
Cited
US3984819A
Cited
US4011545A
Cited
US4149248A
Cited
US4051551A
Cited
US4174514A
Cited
US4247892A
Cited
US4275410A
Cited
US4239312A
Cited
US4293921A
Cited
US4313342A
Cited
US4509195A
Cited
US4507726A
Cited
US4543642A
Cited
US4667308A
Cited
US4739474A
Cited
US4656463A
Cited
US4598400A
Cited
US4814973A
Cited
US4709327A
Cited
US4697247A
Cited
US4621339A
Cited
US4685070A
Cited
US4855903A
Cited
US4660166A
Cited
US4805091A
Cited
US4739476A
Cited
US4720780A
Cited
US4811210A
Cited
US4889122A
Cited
US4747060A
Cited
US4814980A
Cited
US4729095A
Cited
US4809346A
Cited
US4809347A
Cited
US4821220A
Cited
US4876641A
Cited
US4791567A
Cited
US4766534A
Cited
US4827132A
Cited
US4891810A
Cited
US4811214A
Cited
US4796199A
Cited
US4868818A
Cited
US5005120A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-21 | 1996-01-20 | 1996-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-21 | 2000-01-20 | 2000-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-21 | 2004-01-20 | 2004-07-21 | $7700.00 | Window Closed / Lapsed |