US4811201A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interconnect circuit
Assignee: Northrop Grumman Space and Mission Systems Corp
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Filing: 1988-05-09
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Granted: 1989-03-07
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Expires: 2008-05-09
Abstract
Abstract An interconnect circuit for use in a computer system employing horizontal architecture and having multiple resources of which the use must be scheduled in an optimum manner. The interconnect circuit reduces scheduling to a mechanical task by providing multi-word storage capability at each of a plurality of cross-points connected in data flow paths between the computer resources. At each cross-point of the interconnect circuit, data may be written into a selected location and retrieved from a selected location. Writing may be accomplished by an insertion operation in which already stored data is shifted to vacate the location selected for writing. Likewise, reading can be accompanied by a purge operation in which already stored data are shifted into the location from which a data word is purged. In this manner each cross-point can function as a time delay in a data path, to facilitate scheduling of resource usage.
Inventors
- 👤 Bantwal R. Rau
- 👤 Christopher D. Glaeser
- 👤 Philip J. Kuekes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:06
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17375
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
99 words
An interconnect circuit, comprising: a plurality of cross-point modules logically arranged in a switching matrix; a plurality of input ports, each connected to a different selected set of said cross-point modules; and a plurality of output ports, each connected to a different set of said cross-point modules, such that each of said modules is connected to one of said input ports and one of said output ports; and wherein each of said cross-point modules includes a plurality of storage locations for the temporary storage of computational data, and the interconnect circuit connects selected input ports to selected output ports.
Claim 2
Dependent Claim
99 words
An interconnect circuit, comprising: a plurality of cross-point modules logically arranged in a switching matrix; a plurality of input ports, each connected to a different selected set of said cross-point modules; and a plurality of output ports, each connected to a different set of said cross-point modules, such that each of said modules is connected to one of said input ports and one of said output ports; and wherein each of said cross-point modules includes a plurality of storage locations for the temporary storage of computational data, and the interconnect circuit connects selected input ports to selected output ports.
Claim 3
Dependent Claim
19 words
An interconnect circuit as set forth in claim 1, wherein: said cross-point modules are arranged in a rectangular matrix.
Claim 4
Dependent Claim
61 words
An interconnect circuit as set forth in claim 1, wherein each of said cross-point storage modules includes: means for inserting input data into a selected storage location and moving previously stored data to vacate the selected location and maintain the stored data in a single continuous sequence of storage locations; and means for reading output data from a selected storage location.
Claim 5
Dependent Claim
41 words
An interconnect circuit as set forth in claim 3, wherein each of said cross-point modules further includes: means for optionally purging the output data from said circuit and consolidating the remaining stored data into a single continuous sequence of storage locations.
Claim 6
Dependent Claim
75 words
An interconnect circuit as set forth in claim 4, wherein: said data storage locations are arranged in a sequence numbered 0 through n; said means for inserting data functions to shift data stored in locations i through n-1 to locations i+1 through n, respectively, before insertion into location i; and said means for optionally purging functions to shift data from locations k+1 through n to locations k through n-1, respectively, after reading from location k.
Claim 7
Dependent Claim
23 words
An interconnect circuit as set forth in claim 4, wherein: said means for inserting data is operative to write always into location 0.
Claim 8
Dependent Claim
24 words
An interconnect circuit as set forth in claim 4, wherein: said means for inserting data is operative to write into the lowest-numbered unoccupied location.
Claim 9
Dependent Claim
114 words
An interconnect circuit as set forth in claim 4, wherein: each of said storage locations includes a plurality of single-bit storage cells, each of which has a master flip-flop and a slave flip-flop, containing identical data at the beginning and end of a read or write operation; and said circuit performs write and read operations on said master flip-flops, and performs necessary shifting operations under the control of two spaced clock signals, the first of which initiates the shifting of data between master and slave flip-flops of adjacent storage locations, and the second of which initiates the copying of data in an appropriate direction between master and slave flip-flops of the same storage location.
Claim 10
Dependent Claim
77 words
An interconnect circuit as set forth in claim 1, wherein: each input port includes means for selectively enabling one or more of said cross-point modules connected in a set to said input port; and each output port includes means for selecting a cross-point module in the set of modules connected to said output port, means for selecting a storage location in the selected cross-point module, and means for enabling reading from the selected module and selected location.
Claim 11
Dependent Claim
139 words
An interconnect circuit, comprising: a plurality of cross-point modules logically arranged in a rectangular switching matrix, each module having a plurality of storage locations for the temporary storage of computational data; a plurality of input ports, one for each row of modules, for inputting data to selected modules of the circuit, each input port including input storage means coupled to all of the modules in a row, and means for enabling writing and inserting data at selected locations of selected modules in the row; and a plurality of output ports, one for each column of modules, for retrieving data from selected modules of the circuit, each output port including output storage means, and means for enabling reading from selected locations of selected modules in the column; and wherein the interconnect circuit connects selected input ports to selected output ports.
Claim 12
Dependent Claim
139 words
An interconnect circuit, comprising: a plurality of cross-point modules logically arranged in a rectangular switching matrix, each module having a plurality of storage locations for the temporary storage of computational data; a plurality of input ports, one for each row of modules, for inputting data to selected modules of the circuit, each input port including input storage means coupled to all of the modules in a row, and means for enabling writing and inserting data at selected locations of selected modules in the row; and a plurality of output ports, one for each column of modules, for retrieving data from selected modules of the circuit, each output port including output storage means, and means for enabling reading from selected locations of selected modules in the column; and wherein the interconnect circuit connects selected input ports to selected output ports.
Claim 13
Dependent Claim
60 words
An interconnect circuit as set forth in claim 10, wherein each of said cross-point modules includes: means for inserting input data into a selected storage location and moving previously stored data to vacate the selected location and maintain the stored data in a single continuous sequence of storage locations; and means for reading output data from a selected storage location.
Claim 14
Dependent Claim
38 words
An interconnect circuit as set forth in claim 11, wherein each of said cross-point modules further includes: means for optionally purging the output data and consolidating the remaining stored data into a single continuous sequence of storage locations.
Claim 15
Dependent Claim
74 words
An interconnect circuit as set forth in claim 12, wherein: said storage locations are arranged in a sequence numbered 0 through n; said means for inserting data functions to shift data stored in locations i through n-1 to locations i+1 through n, respectively, before insertion into location i; and said means for optionally purging functions to shift data from locations k+1 through n to locations k through n-1, respectively, after reading from location k.
Claim 16
Dependent Claim
23 words
An interconnect circuit as set forth in claim 13, wherein: said means for inserting data is operative to write always into location 0.
Claim 17
Dependent Claim
24 words
An interconnect circuit as set forth in claim 13, wherein: said means for inserting data is operative to write into the lowest-numbered unoccupied location.
Claim 18
Dependent Claim
114 words
An interconnect circuit as set forth in claim 13, wherein: each of said storage locations includes a plurality of single-bit storage cells, each of which has a master flip-flop and a slave flip-flop, containing identical data at the beginning and end of a read or write operation; and said circuit performs write and read operations on said master flip-flops, and performs necessary shifting operations under the control of two spaced clock signals, the first of which initiates the shifting of data between master and slave flip-flops of adjacent storage locations, and the second of which initiates the copying of data in an appropriate direction between master and slave flip-flops of the same storage location.
Claim 19
Dependent Claim
92 words
An interconnect circuit as set forth in claim 10, wherein: said means for enabling reading includes an output control register having a read-enable control field, a module selection field, a word address field and a purge control field; and each of said cross-point modules includes means for purging data read from said module, by shifting other data in said module by one location, to fill the location vacated by the purged data, and means for inserting data into storage after first shifting already stored data to vacate the selected address for writing.
Claim 20
Dependent Claim
46 words
An interconnect circuit as set forth in claim 17, wherein each of said output ports further includes tri-state output means controllable by signals derived from the read-enable control field, to ensure that data are output from said interconnect circuit only when a read-enable sfgnal is active.
Claim 21
Dependent Claim
152 words
A two-by-two crossbar interconnect circuit comprising: four cross-point storage modules, arranged in rows of two to form a switching matrix, and each having sixteen words of storage for the temporary storage of computational data; two input ports connected to the two rows of modules; and two output ports connected to the two columns of modules; wherein each input port includes data input storage means coupled to both modules in its row, and means for coupling a write-enable signal to selected modules in the row; and wherein each output port has output data storage means for holding output from a selected module in the column, and an output control register for providing a module selection signal, a word selection address, and a purge signal for requesting that data from a selected word address and module be purged from the module; and wherein the interconnect circuit connects selected input ports to selected output ports.
Claim 22
Dependent Claim
152 words
A two-by-two crossbar interconnect circuit comprising: four cross-point storage modules, arranged in rows of two to form a switching matrix, and each having sixteen words of storage for the temporary storage of computational data; two input ports connected to the two rows of modules; and two output ports connected to the two columns of modules; wherein each input port includes data input storage means coupled to both modules in its row, and means for coupling a write-enable signal to selected modules in the row; and wherein each output port has output data storage means for holding output from a selected module in the column, and an output control register for providing a module selection signal, a word selection address, and a purge signal for requesting that data from a selected word address and module be purged from the module; and wherein the interconnect circuit connects selected input ports to selected output ports.
Claim 23
Dependent Claim
53 words
An interconnect circuit as set forth in claim 19, wherein each module also includes: data insertion control means for writing data into selected location after first shifting already stored data away from the selected location; and purge control means for shifting already stored data into the location vacated by read and purge data.
Claim 24
Dependent Claim
116 words
For use in a computer of the horizontal type, and interconnect circuit, comprising: a plurality of cross-point modules logically arranged in a geometric switching matrix; a plurality of input ports, each connected to a different selected set of said cross-point modules; and a plurality of output ports, each connected to a different selected set of said cross-point modules, such that each of said modules is connected to one of said input ports and one of said output ports and the interconnect circuit connects selected input ports to selected output ports; and wherein each of said cross-port modules includes a plurality of storage locations, to provide time delays for data routed between processing elements of the computer.
Claim 25
Dependent Claim
116 words
For use in a computer of the horizontal type, and interconnect circuit, comprising: a plurality of cross-point modules logically arranged in a geometric switching matrix; a plurality of input ports, each connected to a different selected set of said cross-point modules; and a plurality of output ports, each connected to a different selected set of said cross-point modules, such that each of said modules is connected to one of said input ports and one of said output ports and the interconnect circuit connects selected input ports to selected output ports; and wherein each of said cross-port modules includes a plurality of storage locations, to provide time delays for data routed between processing elements of the computer.
Claim 26
Dependent Claim
19 words
An interconnect circuit as set forth in claim 21, wherein: said cross-point modules are arranged in a rectangular matrix.
Claim 27
Dependent Claim
61 words
An interconnect circuit as set forth in claim 21, wherein each of said cross-point storage modules includes: means for inserting input data into a selected storage location and moving previously stored data to vacate the selected location and maintain the stored data in a single continuous sequence of ,storage locations; and means for reading output data from a selected storage location.
Claim 28
Dependent Claim
38 words
An interconnect circuit as set forth in claim 23, wherein each of said cross-point modules further includes: means for optionally purging the output data and consolidating the remaining stored data into a single continuous sequence of storage locations.
Claim 29
Dependent Claim
75 words
An interconnect circuit as set forth in claim 24, wherein: said data storage locations are arranged in a sequence numbered 0 through n; said means for inserting data functions to shift data stored in locations i through n-1 to locations i+1 through n, respectively, before insertion into location i; and said means for optionally purging functions to shift data from locations k+1 through n to locations k through n-1, respectively, after reading from location k.
Claim 30
Dependent Claim
23 words
An interconnect circuit as set forth in claim 24, wherein: said means for inserting data is operative to write always into location 0.
Claim 31
Dependent Claim
24 words
An interconnect circuit as set forth in claim 24, wherein: said means for inserting data is operative to write into the lowest-numbered unoccupied location.
Claim 32
Dependent Claim
115 words
An interconnect circuit as set forth in claim 24, wherein: each of said storage locations includes a plurality of single bit storage cells, each of which has a master flip-flop and a slave flip-flop, containing identical data at the beginning and end of a read or write operation; and said circuit performs write and read operations on said master flip-flops, and performs necessary shifting operations under the control of two spaced clock signals, the first of which initiates the shifting of data between master and slave flip-flops of adjacent storage locations, and the second of which initiates the copying of data in an appropriate direction between master and slave flip-flops of the same storage location.
Claim 33
Dependent Claim
77 words
An interconnect circuit as set forth in claim 21, wherein: each input port includes means for selectively enabling one or more of said cross-point modules connected in a set to said input port; and each output port includes means for selecting a cross-point module in the set of modules connected to said output port, means for selecting a storage location in the selected cross-point module, and means for enabling reading from the selected module and selected location.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-06 | 1992-09-05 | 1993-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-06 | 1996-09-05 | 1997-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-06 | 2000-09-05 | 2001-03-07 | $7700.00 | Window Closed / Lapsed |