Multiprocessor system having processors and switches with each pair of processors connected through a single switch using Latin square matrix

Claim 1

A multiprocessor system, comprising: a plurality of processors; and a plurality of switches; each of said processors being connected through a single one of said switches to each other one of said processors, said multiprocessor system having a number of processors N or M, where N is between N k-1 +1 and N k , for a balanced system, and M is between N k-1 -Y k-1 +1 and N k -Y k , for a non-balanced system and k is any positive integer, and N 0 =7 and Y 0 =3, and N k =y k ×(Y k -1)+1, where y k is selected from the set y, where Y={y 1 , y 2 , . . .y k , . . .}, where y 1 =four and y 2 =five and and y k =the kth member of the set Y, which is the set of all integers, in increasing order, which are one greater than a prime number or one greater than a positive integer power of a prime number, each processor has at least y 0 connections and no more than y k connections to related ones of said switches, each switch has at least y 0 connections and no more than y k connections to related ones of said processors in an N processor balanced multiprocessor system, and each switch has at least y 0 connections and no more than y k -1 connections to related ones of said processors in an M processor non-balanced multiprocessor system.