US6069507A
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Circuit and method for reducing delay line length in delay-locked loops
Assignee: Promos Technologies Inc
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Filing: 1998-05-22
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Granted: 2000-05-30
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Expires: 2018-05-22
Abstract
Abstract A digital delay lock loop (DLL) circuit for clock signals with reduced delay line length includes a first phase difference detector for detecting a first phase difference, and a second phase difference detector for detecting a second phase difference. The circuit further includes an inverter for inverting an input clock signal, and a switch controlled by the second phase difference detector for switching between the input clock signal and the inverted input clock signal in accordance with the second phase difference to provide a clock signal to the first phase difference detector. In a method aspect, a method for reducing delay line length in a digital delay locked loop (DLL) includes determining a phase difference between an input clock signal and a feedback clock signal, and maintaining the phase difference between the input clock signal and the feedback clock signal within approximately 180°. The method also includes delaying the input clock signal to compensate for the phase difference, wherein a number of delay cells utilized is reduced by approximately one-half.
Inventors
- 👤 Feng Shen
- 👤 Kunlin Tsai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 02:58
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/087; H03L7/081; H03L7/0812; H03L7/0814; H03L7/0816
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
117 words
A digital delay lock loop (DLL) circuit for clock signals with reduced delay line length, the digital DLL comprising: a first phase difference detector for detecting a first phase difference between a clock signal and a feedback clock signal; a second phase difference detector for detecting a second phase difference between a buffered clock signal and the feedback clock signal; an inverter coupled to the second phase difference detector, the inverter inverting an input clock signal; and a switch controlled by the second phase difference detector for switching between the input clock signal and the inverted input clock signal in accordance with the second phase difference to provide the clock signal to the first phase difference detector.
Claim 2
Dependent Claim
117 words
A digital delay lock loop (DLL) circuit for clock signals with reduced delay line length, the digital DLL comprising: a first phase difference detector for detecting a first phase difference between a clock signal and a feedback clock signal; a second phase difference detector for detecting a second phase difference between a buffered clock signal and the feedback clock signal; an inverter coupled to the second phase difference detector, the inverter inverting an input clock signal; and a switch controlled by the second phase difference detector for switching between the input clock signal and the inverted input clock signal in accordance with the second phase difference to provide the clock signal to the first phase difference detector.
Claim 3
Dependent Claim
15 words
The circuit of claim 1 wherein the first phase difference detector has a first resolution.
Claim 4
Dependent Claim
24 words
The circuit of claim 2 wherein the second phase (difference detector has a second resolution, the second resolution being lower than the first resolution.
Claim 5
Dependent Claim
30 words
The circuit of claim 1 wherein the second phase difference detector controls the switch to select the input clock signal when the second phase difference is less than approximately 180°.
Claim 6
Dependent Claim
31 words
The circuit of claim 4 wherein the second phase difference detector controls the switch to select the inverted input clock signal when the second phase difference is greater than approximately 180°.
Claim 7
Dependent Claim
37 words
The circuit of claim 1 further comprising a shift register controlled by the first phase difference detector and a delay line coupled to the shift register with one shift register cell provided for each delay line cell.
Claim 8
Dependent Claim
16 words
The circuit of claim 1 wherein the first phase difference is maintained between 0° and 180°.
Claim 9
Independent Claim
94 words
A method for reducing delay line length in a digital delay locked loop (DLL), the method comprising: determining a phase difference between an input clock signal and a feedback clock signal; maintaining the phase difference between the input clock signal and the feedback clock signal within approximately 180°, including selecting an inverted input clock signal as the input clock signal when the determined phase difference is greater than approximately 180°; and delaying the input clock signal to compensate for the phase difference, wherein a number of delay cells utilized is reduced by approximately one-half.
Claim 10
Independent Claim
94 words
A method for reducing delay line length in a digital delay locked loop (DLL), the method comprising: determining a phase difference between an input clock signal and a feedback clock signal; maintaining the phase difference between the input clock signal and the feedback clock signal within approximately 180°, including selecting an inverted input clock signal as the input clock signal when the determined phase difference is greater than approximately 180°; and delaying the input clock signal to compensate for the phase difference, wherein a number of delay cells utilized is reduced by approximately one-half.
Claim 11
Dependent Claim
30 words
The method of claim 8 wherein the step of delaying further comprises adjusting the inverted clock signal appropriately with a loop comprising a phase detector, shift register, and delay line.
Claim 12
Independent Claim
99 words
A method for reducing delay line length in a digital delay locked loop (DLL), the method comprising: determining a phase difference between an input clock signal and a feedback clock signal; maintaining the phase difference between the input clock signal and the feedback clock signal approximately 180°, including adjusting the input clock signal with a loop comprising a phase detector, shift register, and delay line when the determined phase difference is less than approximately 180°; and delaying the input clock signal to compensate for the phase difference, wherein a number of delay cells utilized is reduced by approximately one-half.
Claim 13
Independent Claim
99 words
A method for reducing delay line length in a digital delay locked loop (DLL), the method comprising: determining a phase difference between an input clock signal and a feedback clock signal; maintaining the phase difference between the input clock signal and the feedback clock signal approximately 180°, including adjusting the input clock signal with a loop comprising a phase detector, shift register, and delay line when the determined phase difference is less than approximately 180°; and delaying the input clock signal to compensate for the phase difference, wherein a number of delay cells utilized is reduced by approximately one-half.
Claim 14
Dependent Claim
18 words
The method of claim 10 wherein the phase detector comprises a phase difference detector with a first resolution.
Claim 15
Dependent Claim
33 words
The method of claim 11 wherein the step of determining a phase difference occurs through a second phase difference detector with a second resolution, the second resolution being lower than the first resolution.
Claim 16
Independent Claim
66 words
A method for reducing delay line length in a digital delay locked loop (DLL), the method comprising: determining whether a feedback clock signal in the DLL follows within a 180° phase difference behind an input clock signal; and selecting a switch position according to the determining step, including selecting a first switch position when the feedback clock signal follows behind the input clock signal with 180°.
Claim 17
Independent Claim
66 words
A method for reducing delay line length in a digital delay locked loop (DLL), the method comprising: determining whether a feedback clock signal in the DLL follows within a 180° phase difference behind an input clock signal; and selecting a switch position according to the determining step, including selecting a first switch position when the feedback clock signal follows behind the input clock signal with 180°.
Claim 18
Dependent Claim
20 words
The method of claim 13 wherein the first switch position selects the input clock signal for transfer through the DLL.
Claim 19
Dependent Claim
28 words
The method of claim 13 wherein selecting further comprises selecting a second switch position when the feedback clock signal does not follow the input clock signal within 180°.
Claim 20
Dependent Claim
21 words
The method of claim 15 wherein the second switch position selects an inverted input clock signal for transfer through the DLL.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-30 | 2003-11-29 | 2004-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-30 | 2007-11-29 | 2008-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-30 | 2011-11-29 | 2012-05-30 | $7700.00 | Window Closed / Lapsed |