Phase lock loop having a reduced synchronization transfer period

Claim 1

A phase lock loop comprising: a control signal generating section, receiving an input signal and a first signal through first and second inputs of said control signal generating section, respectively, to generate a control signal based on a phase difference between said input signal and said first signal; a variable delay circuit, including a plurality of cascaded variable delay gates wherein each of said cascaded variable delay gates is controlled by the control signal; a frequency divider for supplying a divided signal obtained by dividing the output of said phase lock loop; a phase lock detecting section for detecting a phase difference between said input signal and the output of said variable delay circuit and for generating a phase lock detection signal when said phase difference between said input signal and the output of said variable delay circuit is smaller than a predetermined value; a first switching section for connecting the input of said variable delay circuit to the first input of said control signal generating section in the absence of the phase lock detection signal, the output of said phase lock loop being connected to the output of one of said variable delay gates and for connecting the input of said variable delay circuit to the output of one of said variable delay gates to form a loop for oscillation when said phase lock detection signal is generated by said phase lock detecting section; and a second switching section for connecting the second input of said control signal generating section selectively to the output of said variable delay circuit in the absence of the lock detection signal and for connecting the second input of said control signal generating section to the output of said frequency divider when said phase lock detection signal is generated by said phase lock detecting section.