Patent US6067644A successfully refreshed from Google Patents.
US6067644A
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System and method monitoring instruction progress within a processor
Assignee: International Business Machines Corp
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Filing: 1998-04-15
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Granted: 2000-05-23
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Expires: 2018-04-15
Abstract
Abstract A processor operable for processing an instruction through a plurality of internal stages will produce a result of the processing of the process at each stage or a reason code why the stage was unable to process the instruction. The result or the reason code will then be passed to a subsequent stage, which will attempt to process the instruction. The second stage will forward the reason code when it cannot produce its own result and it is idle. The second stage will create its own reason code when it is not idle but cannot produce a result, and will forward this reason code.
Inventors
- 👤 Frank Eliot Levine
- 👤 Roy Stuart Moore
- 👤 Charles Philip Roth
- 👤 Edward Hugh Welbon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:59
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/28; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3865; G06F11/30; G06F11/34; G06F11/3466; G06F11/348; G06F9/3824; G06F9/3867; G06F2201/00; G06F2201/81; G06F2201/86; G06F2201/88; G06F2201/885
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
121 words
A circuit comprising: first and second sequential stages operable for processing an instruction; circuitry operable for attempting to process the instruction at the first stage; circuitry operable for generating a first reason code at the first stage if the first stage is unable to process the instruction, wherein the first reason code indicates why the first stage could not process the instruction; circuitry operable for forwarding the first reason code from the first stage to the second stage; circuitry operable for creating a second reason code at the second stage indicating an operational state of the second stage; and circuitry operable for forwarding by the second stage to a third stage either the first reason code or the second reason code.
Claim 2
Dependent Claim
121 words
A circuit comprising: first and second sequential stages operable for processing an instruction; circuitry operable for attempting to process the instruction at the first stage; circuitry operable for generating a first reason code at the first stage if the first stage is unable to process the instruction, wherein the first reason code indicates why the first stage could not process the instruction; circuitry operable for forwarding the first reason code from the first stage to the second stage; circuitry operable for creating a second reason code at the second stage indicating an operational state of the second stage; and circuitry operable for forwarding by the second stage to a third stage either the first reason code or the second reason code.
Claim 3
Dependent Claim
31 words
The circuit as recited in claim 1, further comprising: a performance monitor counter operable for performing a counting function as a function of the reason code received at the third stage.
Claim 4
Dependent Claim
23 words
The circuit as recited in claim 2, wherein the counting function increments a counter if the reason code matches a predetermined reason code.
Claim 5
Dependent Claim
31 words
The circuit as recited in claim 1, wherein the second stage forwards the first reason code to the third stage when the second stage cannot produce a result and is idle.
Claim 6
Dependent Claim
24 words
The circuit as recited in claim 1, further comprising circuitry for identifying the instruction causing the second stage to produce the second reason code.
Claim 7
Dependent Claim
43 words
The circuit as recited in claim 1, further comprising: circuitry operable for attempting to process the instruction at the second stage; and circuitry operable for forwarding the second reason code to third stage when the second stage is unable to produce a result.
Claim 8
Independent Claim
107 words
A method comprising the steps of: attempting to process an instruction in a first stage; generating a first reason code at the first stage if the first stage is unable to process the instruction, wherein the first reason code indicates why the first stage could not process the instruction; transferring the first reason code from the first stage to a second stage; and either transferring the first reason code received by the second stage to a third stage subsequent to the second stage or creating a second reason code why the second stage cannot produce a result and forwarding the second reason code to the third stage.
Claim 9
Independent Claim
107 words
A method comprising the steps of: attempting to process an instruction in a first stage; generating a first reason code at the first stage if the first stage is unable to process the instruction, wherein the first reason code indicates why the first stage could not process the instruction; transferring the first reason code from the first stage to a second stage; and either transferring the first reason code received by the second stage to a third stage subsequent to the second stage or creating a second reason code why the second stage cannot produce a result and forwarding the second reason code to the third stage.
Claim 10
Dependent Claim
21 words
The method as recited in claim 7, further comprising the step of identifying and outputting the instruction causing a reason code.
Claim 11
Dependent Claim
28 words
The method as recited in claim 7, further comprising the step of: performing a counting function as a function of the reason code received at the third stage.
Claim 12
Dependent Claim
31 words
The method as recited in claim 7, wherein the second stage transfers the first reason code to the third stage when the second stage is idle and cannot produce a result.
Claim 13
Dependent Claim
37 words
The method as recited in claim 7, further comprising the steps of the second stage producing a result and forwarding the result to the third stage even when the second stage has received the first reason code.
Claim 14
Dependent Claim
241 words
A processor comprising: first, second, and third sequential stages operable for processing an instruction; circuitry operable for attempting to process the instruction at the first stage; circuitry operable for either producing a first result of the processing of the instruction at the first stage or generating a first reason code at the first stage if the first stage is unable to process the instruction, wherein the first reason code indicates why the first stage could not process the instruction; circuitry operable for transferring either the first result or the first reason code from the first stage to the second stage; circuitry operable for attempting to process the instruction at the second stage when the first result is received; circuitry operable for either producing a second result of the processing of the instruction at the second stage or generating a second reason code at the second stage if the second stage is unable to process the instruction, wherein the second reason code indicates why the second stage could not process the instruction; circuitry operable for transferring the first reason code received from the first stage to a third stage subsequent to the second stage if the second stage received the first reason code from the first stage and the second stage is idle; and circuitry operable for transferring the second reason code to the third stage subsequent to the second stage if the second stage was unable to process the first result.
Claim 15
Dependent Claim
241 words
A processor comprising: first, second, and third sequential stages operable for processing an instruction; circuitry operable for attempting to process the instruction at the first stage; circuitry operable for either producing a first result of the processing of the instruction at the first stage or generating a first reason code at the first stage if the first stage is unable to process the instruction, wherein the first reason code indicates why the first stage could not process the instruction; circuitry operable for transferring either the first result or the first reason code from the first stage to the second stage; circuitry operable for attempting to process the instruction at the second stage when the first result is received; circuitry operable for either producing a second result of the processing of the instruction at the second stage or generating a second reason code at the second stage if the second stage is unable to process the instruction, wherein the second reason code indicates why the second stage could not process the instruction; circuitry operable for transferring the first reason code received from the first stage to a third stage subsequent to the second stage if the second stage received the first reason code from the first stage and the second stage is idle; and circuitry operable for transferring the second reason code to the third stage subsequent to the second stage if the second stage was unable to process the first result.
Claim 16
Dependent Claim
15 words
The processor as recited in claim 12, wherein the third stage is a completion stage.
Claim 17
Dependent Claim
17 words
The processor as recited in claim 12, wherein the third stage includes circuitry for accumulating reason codes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-23 | 2003-11-22 | 2004-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-23 | 2007-11-22 | 2008-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-23 | 2011-11-22 | 2012-05-23 | $7700.00 | Window Closed / Lapsed |