Patent US3032364A successfully refreshed from Google Patents.
US5481683A
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Super scalar computer architecture using remand and recycled general purpose register to manage out-of-order execution of instructions
Assignee: International Business Machines Corp
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Filing: 1993-03-19
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Granted: 1996-01-02
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Expires: 2013-03-19
Abstract
Abstract A super scalar computer architecture and method of operation for executing instructions out-of-order while managing for data dependencies, data anti-dependencies, and integrity of sequentiality for precise interrupts, restarts and branch deletions. Multiple registers and tables are used to rename and recycle source and destination addresses referenced to a general purpose register. Access to destination data in the general purpose register is locked until the instruction associated with the data is fully executed. Renaming of both the source and destination registers avoids anti-dependency problems while integrity of sequentiality is maintained by ordered retirement of instruction results consistent with the order of the input instructions. The system and method operate with multiple input instructions and multiple execution units. The control words generated by the renaming of the source and destination registers differ insignificantly from the original instructions, obviating the practice of adding status and sequence information to processor control words.
Inventors
- 👤 Faraydon Karim
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:50
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/384; G06F15/00; G06F15/76; G06F15/78; G06F9/30145; G06F9/3854; G06F9/3856; G06F9/3858; G06F9/3861; G06F9/3863
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
189 words
A super scalar computer architecture for executing instructions out-of-order with at least several instructions performing computations on data in computer architected registers, comprising: a source of instructions which are arranged in an order that the instructions are to be executed; a multiplicity of execution units for executing control words; a plurality of general purpose registers for storing control word data by address; means for forming control words, for transmission to available execution units, by replacing any specified computer architected register with a renamed and recycled register address referenced to a general purpose register; collision vector table means for storing control word execution status and for providing register addresses to the means for forming control words in a sequence matching the order that the instructions are to be executed, the collision vector table means has a table size defined by the difference between the number of general purpose registers and the number of computer architected registers; and means for using the collision vector table means to recycle general purpose register addresses responsive to the execution of control words in the execution units to thereby allow for out-of-order control word execution.
Claim 2
Dependent Claim
189 words
A super scalar computer architecture for executing instructions out-of-order with at least several instructions performing computations on data in computer architected registers, comprising: a source of instructions which are arranged in an order that the instructions are to be executed; a multiplicity of execution units for executing control words; a plurality of general purpose registers for storing control word data by address; means for forming control words, for transmission to available execution units, by replacing any specified computer architected register with a renamed and recycled register address referenced to a general purpose register; collision vector table means for storing control word execution status and for providing register addresses to the means for forming control words in a sequence matching the order that the instructions are to be executed, the collision vector table means has a table size defined by the difference between the number of general purpose registers and the number of computer architected registers; and means for using the collision vector table means to recycle general purpose register addresses responsive to the execution of control words in the execution units to thereby allow for out-of-order control word execution.
Claim 3
Dependent Claim
35 words
The architecture recited in claim 1, wherein the means for recycling general purpose register addresses updates the collision vector table means upon execution of control words in the order the instructions are to be executed.
Claim 4
Dependent Claim
30 words
The architecture recited in claim 2, wherein the means for forming control words generates control words comprising an opcode, renamed source addresses, and collision vector table means recycled destination addresses.
Claim 5
Dependent Claim
27 words
The architecture recited in claim 1, wherein the collision vector table means comprises sub-tables which coincide in size to the number of instructions fetched during a cycle.
Claim 6
Dependent Claim
30 words
The architecture recited in claim 4, wherein the means for forming control words generates control words composing an opcode, renamed source addresses, and collision vector table means recycled destination addresses.
Claim 7
Dependent Claim
24 words
The architecture recited in claim 1, wherein the means for recycling general purpose register addresses distinguishes by tag control words derived from speculative instructions.
Claim 8
Dependent Claim
31 words
The architecture recited in claim 1, wherein the means for recycling general purpose register addresses distinguishes by tag control words derived from instructions corresponding to different paths after a branch instruction.
Claim 9
Independent Claim
205 words
A method of operating a super scalar architecture computer to allow out-of-order execution of input instructions with at least several instructions performing computations on data in computer architected registers, comprising the steps of: providing instructions in an order that the instructions are to be executed; forming control words for transmission to available execution units of a multiplicity of computer execution units which execute control words by: renaming source register addresses of multiple input instructions using a first rename table to replace specified computer architected registers with renamed and recycled register addresses referenced to general purpose registers, from a plurality of general purpose registers for storing control word data by address; and renaming destination register addresses of multiple input instructions using recycled addresses from a collision vector table storing control word status in a sequence matching the order that the instructions are to be executed, the table size defined by the difference between the number of general purpose registers and the number of computer architected registers; processing control words composed of renamed source register addresses and renamed destination register addresses using available execution units; and recycling general purpose register addresses using the collision vector table responsive to executing control words to allow out-of-order control word execution.
Claim 10
Independent Claim
205 words
A method of operating a super scalar architecture computer to allow out-of-order execution of input instructions with at least several instructions performing computations on data in computer architected registers, comprising the steps of: providing instructions in an order that the instructions are to be executed; forming control words for transmission to available execution units of a multiplicity of computer execution units which execute control words by: renaming source register addresses of multiple input instructions using a first rename table to replace specified computer architected registers with renamed and recycled register addresses referenced to general purpose registers, from a plurality of general purpose registers for storing control word data by address; and renaming destination register addresses of multiple input instructions using recycled addresses from a collision vector table storing control word status in a sequence matching the order that the instructions are to be executed, the table size defined by the difference between the number of general purpose registers and the number of computer architected registers; processing control words composed of renamed source register addresses and renamed destination register addresses using available execution units; and recycling general purpose register addresses using the collision vector table responsive to executing control words to allow out-of-order control word execution.
Claim 11
Dependent Claim
29 words
The method recited in claim 6 further including the step of: locking access to data in destination registers until register related data is generated by the corresponding execution unit.
Claim 12
Dependent Claim
38 words
The method recited in claim 9, further comprising the step of: upon entry of register related data, unlocking access to the corresponding destination register and setting a finish flag in a corresponding entry off the collision vector table.
Claim 13
Dependent Claim
39 words
The method recited in claim 10, further comprising the step of: recycling general purpose register addresses between the collision vector table and a second rename table in sequence with the completion of instructions in the order of their input.
Claim 14
Dependent Claim
49 words
The method recited in claim 8, further comprising the steps of: distinguishing, by tags related to control word addresses, the control word addresses attributed to speculative instructions; and selectively delaying the recycling of general purpose register addresses distinguished by tags until a branch associated with speculative instructions is resolved.
Claim 15
Dependent Claim
172 words
A data processing system for executing an ordered list of instructions with at least several instructions performing computations on data in architected registers, said system comprising: a plurality of general purpose registers storing data; a plurality of rename registers corresponding to the architected registers and containing addresses of general purpose registers; control word means for providing a control word in place of each instruction, each control word having any specified architected register replaced by a general purpose register address contained in its corresponding rename register; a plurality of execution units for executing control words on data from said general purpose registers; and regulation means for regulating execution of control words in each execution unit maintaining ordered instruction data integrity in said general purpose registers through an assignment of general while providing out of order control word execution, said regulation means including means for storing control word execution status in a table of a size defined by the difference between the number of general purpose registers and the number of computer architected registers.
Claim 16
Dependent Claim
172 words
A data processing system for executing an ordered list of instructions with at least several instructions performing computations on data in architected registers, said system comprising: a plurality of general purpose registers storing data; a plurality of rename registers corresponding to the architected registers and containing addresses of general purpose registers; control word means for providing a control word in place of each instruction, each control word having any specified architected register replaced by a general purpose register address contained in its corresponding rename register; a plurality of execution units for executing control words on data from said general purpose registers; and regulation means for regulating execution of control words in each execution unit maintaining ordered instruction data integrity in said general purpose registers through an assignment of general while providing out of order control word execution, said regulation means including means for storing control word execution status in a table of a size defined by the difference between the number of general purpose registers and the number of computer architected registers.
Claim 17
Dependent Claim
48 words
The system recited in claim 13, further comprising: means for identifying by tags related to control words one or more control words attributed to speculative instructions of a branch; and means for using the tags to selectively delay operations of the regulation means until the branch is resolved.
Claim 18
Dependent Claim
44 words
The system recited in claim 13, further comprising: means for identifying by tags related to control words one or more control words attributed to different branches; and means for using the tags to select control words subject to the regulation means following branch resolution.
Claim 19
Dependent Claim
190 words
A data processing system for executing an ordered list of instructions with at least several instructions performing computations on data in architected registers, said system comprising: a plurality of general purpose registers storing data, each register including means for indicating it is to receive data; a plurality of rename registers corresponding to the architected registers and containing addresses of general purpose registers; control word means for providing a control word in place of each instruction, each control word having any specified architected register replaced by a general purpose register address contained in its corresponding rename register; a plurality of execution units for executing control words on data from said general purpose registers; and regulation means for regulating execution of control words in each execution unit maintaining ordered instruction data integrity in said general purpose registers through an assignment of general purpose registers in an order matching the ordered list of instructions while providing out of order control word execution, said regulation means storing control word execution status in a table having a size defined by the difference between the number of general purpose registers and the number of architected registers.
Claim 20
Dependent Claim
190 words
A data processing system for executing an ordered list of instructions with at least several instructions performing computations on data in architected registers, said system comprising: a plurality of general purpose registers storing data, each register including means for indicating it is to receive data; a plurality of rename registers corresponding to the architected registers and containing addresses of general purpose registers; control word means for providing a control word in place of each instruction, each control word having any specified architected register replaced by a general purpose register address contained in its corresponding rename register; a plurality of execution units for executing control words on data from said general purpose registers; and regulation means for regulating execution of control words in each execution unit maintaining ordered instruction data integrity in said general purpose registers through an assignment of general purpose registers in an order matching the ordered list of instructions while providing out of order control word execution, said regulation means storing control word execution status in a table having a size defined by the difference between the number of general purpose registers and the number of architected registers.
Claim 21
Dependent Claim
26 words
A data processing system according to claim 16 wherein said register indicating means includes means to lock access to the register until the register receives data.
References Cited (Backward Citations)
US3346851A
Cited
US4574349A
Cited
US4807115A
Cited
US4847755A
Cited
US4903196A
Cited
EP0301220A2
Cited
US4901233A
Cited
US5134561A
Cited
US4972470A
Cited
US5133077A
Cited
US5155817A
Cited
EP0432774A2
Cited
US5280615A
Cited
US5197132A
Cited
US5261071A
Cited
US5355457A
Cited
US5386562A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-01 | 1999-07-03 | 2000-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-01 | 2003-07-03 | 2004-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-01 | 2007-07-03 | 2008-01-02 | $7700.00 | Window Closed / Lapsed |