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US6065106A
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Resuming normal execution by restoring without refetching instructions in multi-word instruction register interrupted by debug instructions loading and processing
Assignee: Texas Instruments Inc
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Filing: 1997-11-19
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Granted: 2000-05-16
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Expires: 2017-11-19
Abstract
Abstract A data processing system on an integrated circuit 42 with microprocessor 1 and peripheral devices 60-61 is provided with an emulation unit 50 which allows debugging and emulation of integrated circuit 42 when connected to an external test system 51. Microprocessor 1 has in instruction execution pipeline which has several execution phases which involve fetch/decode units 10a-c and functional execution units 12, 14, 16 and 18. The pipeline of microprocessor 1 is unprotected so that memory access latency to data memory 22 and register file 20 can be utilized by system program code which is stored in instruction memory 23. Emulation unit 50 provides means for emulating the unprotected pipeline of microprocessor 1 and for rapidly uploading and downloading memories 22-23. During emulation, the fetching of instructions from program memory can be halted. A packet of instructions can be transferred from the emulation unit to the instruction register of the processor via a test port and executed without fetching instructions from instruction memory. The packet of instructions can perform various tasks, such as loading or storing data or loading new instructions into program memory. Emulation unit 50 operates in a manner to prevent extraneous operations from occurring which could otherwise affect memories 22-23 or peripheral devices 60-61 during emulation.
Inventors
- 👤 Douglas E. Deao
- 👤 Natarajan Seshan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:41
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/355; G06F9/3552; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/31705; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318566; G06F11/00; G06F11/36; G06F11/362; G06F11/3648; G06F9/30003; G06F9/3005; G06F9/30098; G06F9/30101; G06F9/30105; G06F9/30112; G06F9/30116; G06F9/3012; G06F9/30134; G06F9/38; G06F9/3836; G06F9/3842; G06F9/3853
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
151 words
A method for debugging a processor within a data processing system, the processor having a multi-word instruction register, comprising the steps of: executing system code from the multi-word instruction register in an instruction execution pipeline in a normal operational manner; halting the normal operation of the processor by saying at least a first partially executed instruction to an external test system; inhibiting fetching of instructions into the multi-word instruction register; transferring a first sequence of debug code instructions into the multi-word instruction register from the external test system; executing the sequence of debug code instructions in the processor's multi-word instruction register to perform a debug operation on the processor; and resuming execution of the system code in the multi-word instruction register by restoring at least the first partially executed instruction to the multi-word instruction register from the external test system, enabling fetching of instructions and starting normal operation of the processor.
Claim 2
Independent Claim
151 words
A method for debugging a processor within a data processing system, the processor having a multi-word instruction register, comprising the steps of: executing system code from the multi-word instruction register in an instruction execution pipeline in a normal operational manner; halting the normal operation of the processor by saying at least a first partially executed instruction to an external test system; inhibiting fetching of instructions into the multi-word instruction register; transferring a first sequence of debug code instructions into the multi-word instruction register from the external test system; executing the sequence of debug code instructions in the processor's multi-word instruction register to perform a debug operation on the processor; and resuming execution of the system code in the multi-word instruction register by restoring at least the first partially executed instruction to the multi-word instruction register from the external test system, enabling fetching of instructions and starting normal operation of the processor.
Claim 3
Dependent Claim
71 words
The method of claim 1, wherein the step of executing debug code further comprises: executing the sequence of debug code in a normal operational manner to access first data in a first memory circuit internal to the processor and to store the first data in at least a first memory element of the processor; and transferring the first data from the first memory element to a test port on the processor.
Claim 4
Dependent Claim
28 words
The method of claim 2, wherein the step of halting the normal operation further comprises receiving a debug command via the test port from the external debug system.
Claim 5
Dependent Claim
46 words
The method of claim 3, wherein the step of executing the sequence of debug code in a normal operational manner further comprises sending a notification via the test port to the external test system in response to executing an instruction of the sequence of debug code.
Claim 6
Dependent Claim
33 words
The method of claim 4, wherein the steps of halting, executing debug code, and resuming execution of the system code does not cause a previously fetched instruction to be refetched from program memory.
Claim 7
Dependent Claim
36 words
The method of claim 5 wherein the step of transferring the first data further comprises transferring the first data from the first memory element via a serial scan path to the test port on the processor.
Claim 8
Dependent Claim
22 words
The method of claim 1, wherein the step of halting comprises saving a first state of the contents the instruction execution pipeline.
Claim 9
Dependent Claim
65 words
The method of claim 7, wherein the step of halting further comprises stepping the instruction execution pipeline one pipeline phase and saving a second state of the contents the instruction execution pipeline; and repeating the step of stepping one pipeline phase and saving a further state of contents of the instruction execution pipeline until the system code instructions are flushed from the instruction execution pipeline.
Claim 10
Dependent Claim
35 words
The method of claim 8, wherein the step of resuming execution comprises restoring the first state of the contents of the instruction pipeline into the instruction pipeline before normal operation of the processor is started.
Claim 11
Dependent Claim
54 words
The method of claim 9, wherein the step of executing debug code further comprises executing the sequence of debug code in a normal operational manner to access first data in a first memory circuit internal to the processor and to store the first data in at least a first memory element of the processor.
Claim 12
Dependent Claim
26 words
The method of claim 10, further comprising the step of transferring the first data from the first memory element to a test port on the processor.
Claim 13
Dependent Claim
47 words
The method of claim 11, wherein the step of executing the sequence of debug code in a normal operational manner further comprises sending a first notification via the test port to the external debug system in response to executing an instruction of the sequence of debug code.
Claim 14
Dependent Claim
48 words
The method of claim 12, further comprising the steps of transferring a second sequence of debug code instructions into the multi-word instruction register from the external debug system in response to the first notification and executing the second sequence of debug code while fetching of instruction remains inhibited.
Claim 15
Dependent Claim
33 words
The method of claim 13, wherein the steps of halting, executing debug code, and resuming execution of the system code does not cause a previously fetched instruction to be refetched from program memory.
Claim 16
Dependent Claim
36 words
The method of claim 14 wherein the step of transferring the first data further comprises transferring the first data from the first memory element via a serial scan path to the test port on the processor.
Claim 17
Dependent Claim
188 words
A data processing system comprising a microprocessor which has a multi-word instruction register, the microprocessor further comprising: an instruction execution pipeline connected to the multi-word instruction register for executing system code from the multi-word instruction register in a normal operational manner; emulation circuitry connected to the instruction execution pipeline and to the multi-word instruction register for halting the normal operation of the processor by saving at least a first partially executed instruction to an external test system, the emulation circuitry operable to inhibit fetching of instructions into the multi-word instruction register and to transfer a first sequence of debug code into the multi-word instruction register from the external debug system and further operable to restore at least the fit partially executed instruction to the multi-word instruction register from the external test system and to enable fetching of instructions; and wherein the instruction execution pipeline is further operable to execute the first sequence of debug code in the processor's multi-word instruction register to perform a debug operation on the processor and to then resume execution of the restored at least first partially executed instruction in the multi-word instruction register.
Claim 18
Dependent Claim
188 words
A data processing system comprising a microprocessor which has a multi-word instruction register, the microprocessor further comprising: an instruction execution pipeline connected to the multi-word instruction register for executing system code from the multi-word instruction register in a normal operational manner; emulation circuitry connected to the instruction execution pipeline and to the multi-word instruction register for halting the normal operation of the processor by saving at least a first partially executed instruction to an external test system, the emulation circuitry operable to inhibit fetching of instructions into the multi-word instruction register and to transfer a first sequence of debug code into the multi-word instruction register from the external debug system and further operable to restore at least the fit partially executed instruction to the multi-word instruction register from the external test system and to enable fetching of instructions; and wherein the instruction execution pipeline is further operable to execute the first sequence of debug code in the processor's multi-word instruction register to perform a debug operation on the processor and to then resume execution of the restored at least first partially executed instruction in the multi-word instruction register.
Claim 19
Dependent Claim
35 words
The data processing system of claim 16, wherein the emulation circuitry is further operable to save a first state of the contents of the instruction execution pipeline after halting the normal operation of the processor.
Claim 20
Dependent Claim
38 words
The data processing system of claim 17, wherein the emulation circuitry is further operable to restore the first state of the contents of the instruction pipeline into the instruction pipeline before normal operation of the processor is resumed.
Claim 21
Dependent Claim
55 words
The data processing system of claim 18, wherein the instruction execution pipeline circuitry is further operable to execute a software breakpoint instruction in the sequence of debug code and to transfer a second sequence of debug code into the multi-word instruction register from an external test system in response to executing the software breakpoint instruction.
Claim 22
Dependent Claim
19 words
The data processing system of claim 19, further comprising program memory for holding program instructions connected to the microprocessor.
Claim 23
Dependent Claim
42 words
The data processing system of claim 20, wherein the instruction execution pipeline is further operable to resume execution of system code in a normal operational manner after executing the first sequence of debug code without refetching an instruction from the program memory.
Claim 24
Dependent Claim
18 words
The data processing system of claim 21, further comprising a plurality of peripheral devices connected to the microprocessor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-16 | 2003-11-15 | 2004-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-16 | 2007-11-15 | 2008-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-16 | 2011-11-15 | 2012-05-16 | $7700.00 | Window Closed / Lapsed |