US6064588A
Expired / Lapsed
US
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Embedded dram with noise-protected differential capacitor memory cells
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1998-03-30
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Granted: 2000-05-16
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Expires: 2018-03-30
Abstract
Abstract A logically complementary pair of charge storage capacitors are employed in each memory cell of an embedded dynamic random access memory (DRAM) segment. The complementary capacitors establish a data bit signal from each cell by a relative difference in charge stored on the capacitors. The adverse influences of noise are reduced or eliminated because the noise will generally equally effect both of the complementary capacitors, as well as complementary bit lines connected to the capacitors. Differential sensing of the bit line signals also avoids the influence of noise. A capacitor reference potential conductor distributes substantially equal capacitor reference voltage to each capacitor to allow each capacitor to charge and discharge more uniformly under the influence of noise.
Inventors
- 👤 Harold S. Crafts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 10:28
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/50; G; G11; G11C; G11C5/00; G11C5/005; G11C5/14; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10D84/992
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
54 words
A dynamic random access memory (DRAM) segment formed by a plurality of memory cells embedded in a system level integrated circuit (SLIC), wherein each memory cell includes a logically complementary pair of charge storage capacitors which establish a data bit signal from each cell by a relative difference in charge stored on the capacitors.
Claim 2
Dependent Claim
54 words
A dynamic random access memory (DRAM) segment formed by a plurality of memory cells embedded in a system level integrated circuit (SLIC), wherein each memory cell includes a logically complementary pair of charge storage capacitors which establish a data bit signal from each cell by a relative difference in charge stored on the capacitors.
Claim 3
Dependent Claim
50 words
A DRAM segment as defined in claim 1 wherein the plurality of memory cells are formed on a substrate of the SLIC, and further comprising: an isolation structure formed in the substrate to electrically isolate the complementary charge storage capacitors from charges created by noise signals conducted in the substrate.
Claim 4
Dependent Claim
50 words
A DRAM segment as defined in claim 2 wherein substrate is formed of material with a majority of one type of positive or negative carriers, and the isolation structure further comprises: a well of the other majority carrier type formed in substrate and containing therein each of the memory cells.
Claim 5
Dependent Claim
34 words
A DRAM segment as defined in claim 2 further comprising: a well conductor connected to the well at a plurality of spaced-apart locations throughout the well to equally distribute electrical voltages throughout the well.
Claim 6
Dependent Claim
19 words
A DRAM segment as defined in claim 4 wherein the well conductor comprises a mesh of intersecting connected conductors.
Claim 7
Dependent Claim
28 words
A DRAM segment as defined in claim 5 further comprising: means for connecting the well conductor to a quiet, substantially isolated, power supply external to the DRAM segment.
Claim 8
Dependent Claim
31 words
A DRAM segment as defined in claim 5 wherein the mesh is located in a position spaced above the substrate on the opposite side of the memory cells from the well.
Claim 9
Dependent Claim
46 words
A DRAM segment as defined in claim 7 further comprising: a pair of complementary bit lines extending from each cell, each bit line connected to a different one of the capacitors, and each bit line positioned between the mesh and the memory cells on the substrate.
Claim 10
Dependent Claim
80 words
A DRAM segment as defined in claim 7 wherein the plurality of memory cells are formed in a matrix on the substrate, each memory cell further includes a transistor connected to the charge storage capacitor, and the transistor has a gate, and further comprising: a plurality of word lines extending across and connecting to gates of the transistors in memory cells in rows of the matrix, each word line positioned between the mesh and the memory cells on the substrate.
Claim 11
Dependent Claim
59 words
A DRAM segment as defined in claim 1 wherein the plurality of memory cells are formed in a matrix on a substrate of the SLIC, and each charge storage capacitor further includes plates, and further comprising: a plurality of referencing conductors extending over the matrix and above the substrate and connecting to a reference potential plate of each capacitor.
Claim 12
Dependent Claim
30 words
A DRAM segment as defined in claim 10 further comprising: means for connecting the capacitor reference potential conductor to a quiet, substantially isolated, power supply external to the DRAM segment.
Claim 13
Dependent Claim
27 words
A DRAM segment as defined in claim 10 wherein the plurality of conductors connected to the capacitor reference potential conductor intersect with and connect to one another.
Claim 14
Dependent Claim
26 words
A DRAM segment as defined in claim 12 wherein the plurality of intersecting and connected conductors comprise a mesh which overlays the matrix of memory cells.
Claim 15
Dependent Claim
89 words
A DRAM segment as defined in claim 10 further comprising: a capacitor reference potential conductor extending across memory cells in rows of the matrix and commonly forming the reference potential plates of the charge storage capacitors of the cells across which the capacitor reference potential conductor extends, the reference potential conductor distributing a substantially equal capacitor reference voltage to each capacitor reference potential plate of the row; and a plurality of electrical connections at spaced apart locations between the capacitor reference potential conductor and the plurality of referencing conductors.
Claim 16
Dependent Claim
37 words
A DRAM segment as defined in claim 14 further comprising: a plurality of electrical connections connecting the capacitor reference potential conductor to the plurality of referencing conductors at plurality of spaced apart locations distributed over the matrix.
Claim 17
Dependent Claim
34 words
A DRAM segment as defined in claim 15 wherein the plurality of referencing conductors intersect with and connect to one another to form a mesh, and the mesh overlays the matrix of memory cells.
Claim 18
Dependent Claim
28 words
A DRAM segment as defined in claim 15 wherein the capacitor reference potential conductor is formed substantially of polysilicon and the referencing conductors are formed substantially of metal.
Claim 19
Dependent Claim
60 words
A DRAM segment as defined in claim 1 wherein: the memory cells are formed in a matrix, and further comprising: an integrally continuous shielding conductor which is spaced from and overlays the memory cells in the matrix; and means for connecting the shielding conductor to an external power supply to shield the memory cells of the matrix from electrical noise.
Claim 20
Dependent Claim
32 words
A DRAM segment as defined in claim 18 further comprising: at least one additional layer of electrical conductors spaced above the shielding conductor, the additional layer of electrical conductors conducting electrical signals.
Claim 21
Dependent Claim
44 words
A DRAM segment as defined in claim 19 wherein the SLIC has a plurality of functional components in addition to the DRAM segment, and the electrical conductors of the additional layer are part of one of a signal conducting bus or power conducting conductors.
Claim 22
Dependent Claim
60 words
A DRAM segment as defined in claim 1, wherein each capacitor of each memory cell is connected to a transistor to conduct charge to and conduct charge from the memory cell capacitor, and each capacitor of each memory cell includes an oxide dielectric material which is formed between plates of the capacitor and simultaneously with a gate of the transistor.
References Cited (Backward Citations)
US4866676A
Cited
US5208778A
Cited
US5502675A
Cited
US5386386A
Cited
US5375095A
Cited
US5270977A
Cited
US5323348A
Cited
US5388104A
Cited
US5231319A
Cited
US5325334A
Cited
US5373472A
Cited
US5623640A
Cited
US5517450A
Cited
US5471482A
Cited
US5440517A
Cited
US5694355A
Cited
US5689466A
Cited
US5668755A
Cited
US5650975A
Cited
US5577004A
Cited
US5825682A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-16 | 2003-11-15 | 2004-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-16 | 2007-11-15 | 2008-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-16 | 2011-11-15 | 2012-05-16 | $7700.00 | Window Closed / Lapsed |