Format sensitive timing calibration for an integrated circuit tester

Claim 2

An integrated circuit tester for implementing a succession of timed test events at terminals of an integrated circuit device under test (DUT) during successive test cycles, the apparatus comprising: pattern generation means for producing for each test cycle a separate set of timing data and format data corresponding to each of the DUT terminals; and a plurality of timing signal generators, each corresponding to a separate one of the DUT terminals, each receiving the corresponding set of timing data and format data from said pattern generation means for each test cycle and each producing an output timing signal during each test cycle, wherein the timing data indicates a time interval, wherein the format data references a test event to be triggered by the output timing signal, and wherein each timing signal generator generates its output timing signal following the start of each test cycle with a delay determined in accordance with a combination of its received timing data and format data.

Claim 3

An integrated circuit tester in accordance with claim 1 wherein each timing signal generator comprises: means for producing a signal pulse following the start of each test cycle by an interval indicated by the received timing data, a random access memory (RAM) addressed by said format data, for storing calibration data at each of a plurality of addressable memory locations, and for reading out calibration data when addressed; and a programmable delay circuit for delaying said signal pulse by a time determined in response to calibration data read out of said RAM.

Claim 4

An integrated circuit tester in accordance with claim 1 wherein each timing signal generator comprises: a first random access memory (RAM) addressed by the received timing data and storing timing control data at each of a plurality of addressable storage locations, said first RAM reading out stored timing control data addressed by said timing data; a second RAM addressed by said format data and storing calibration data at each of a plurality of addressable memory locations, said second RAM reading out stored calibration data addressed by said format data; and means for generating said timing signal following the start of each test cycle with a delay determined in accordance with a combination of the timing control data read out of said first RAM and the calibration data read out of said second RAM.

Claim 5

The integrated circuit tester in accordance with claim 3 further comprising means corresponding to each timing signal generator for receiving the output timing signal produced thereby, for receiving the same format data received by the corresponding timing signal generator, and for implementing a test event referenced by the received format data upon receiving the output timing signal.

Claim 6

The integrated circuit tester in accordance with claim 1 further comprising means corresponding to each timing signal generator for receiving the output timing signal produced thereby, for receiving the same format data received by the corresponding timing signal generator, and for implementing a test event referenced by the received format data upon receiving the output timing signal.

Claim 7

An integrated circuit tester in accordance with claim 1 wherein each timing signal generator comprises: a first random access memory (RAM) addressed by said timing data and storing first timing control data at each of a plurality of addressable storage locations, said first RAM reading out stored timing control data when addressed by said timing data, wherein the read out timing control data consists of first and second portions; a second RAM addressed by said format data and storing calibration data at each of a plurality of addressable memory locations, said second RAM reading out stored calibration data addressed by said format data; a counter for generating an output pulse when a number of cycles of an input clock signal occurring since the start of each test cycle reaches a limit indicated by said first portion of said timing control data read out of said first RAM; means for logically combining the calibration data read out of said second RAM with the second portion of the timing control data read out of said first RAM to produce delay control data; and means for delaying the counter output pulse by a time determined by said delay control data thereby to produce said output timing signal.

Claim 8

The integrated circuit tester in accordance with claim 6 further comprising means corresponding to each timing signal generator for receiving the output timing signal produced thereby, for receiving the same format data received by the corresponding timing signal generator, and for implementing a test event referenced by the received format data upon receiving the output timing signal.

Claim 9

An integrated circuit tester for implementing a succession of timed test events at terminals of an integrated circuit device under test (DUT) during successive test cycles, the apparatus comprising: pattern generation means for producing period data and a plurality of sets of format and timing data for each test cycle, the period data indicating the duration of the test cycle, each set of timing and format data corresponding to a separate DUT terminal, the format data referencing a test event to be carried out at the corresponding terminal during the test cycle, and the timing data referencing a time interval; period generator means receiving the period data produced by said pattern generation means and generating in response thereto a period generator output indicating a start of each test cycle; and a plurality of timing signal generators, each corresponding to a separate one of the DUT terminals, each receiving a corresponding set of timing data and format data from said pattern generation means at the start of each test cycle, each receiving the period generator output, and each generating an output timing signal following the start of the test cycle with a first delay determined in accordance with a combination of the received timing data and format data.

Claim 10

An integrated circuit tester for implementing a succession of timed test events at terminals of an integrated circuit device under test (DUT) during successive test cycles, the apparatus comprising: pattern generation means for producing period data and a plurality of sets of format and timing data for each test cycle, the period data indicating the duration of the test cycle, each set of timing and format data corresponding to a separate DUT terminal, the format data referencing a test event to be carried out at the corresponding terminal during the test cycle, and the timing data referencing a time interval; period generator means receiving the period data produced by said pattern generation means and generating in response thereto a period generator output indicating a start of each test cycle; and a plurality of timing signal generators, each corresponding to a separate one of the DUT terminals, each receiving a corresponding set of timing data and format data from said pattern generation means at the start of each test cycle, each receiving the period generator output, and each generating an output timing signal following the start of the test cycle with a first delay determined in accordance with a combination of the received timing data and format data.

Claim 11

An integrated circuit tester in accordance with claim 8 wherein each timing signal generator comprises: means for producing a signal pulse following the start of each test cycle indicated by the received period generator output by with a second delay by the received timing data, a random access memory (RAM) addressed by said format data, for storing calibration data at each of a plurality of addressable memory locations, and for reading out calibration data when addressed; and a programmable delay circuit for delaying said signal pulse by a time determined in response to calibration data read out of said RAM.

Claim 12

An integrated circuit tester in accordance with claim 8 wherein said period generator output comprises a beginning of cycle (BOC) signal pulse indicating that a next test cycle is to begin following a next pulse of an input master clock signal, and wherein said period generator output also comprises period start data indicating an interval between said next pulse of said master clock signal and the start of said next test cycle.

Claim 13

The integrated circuit tester in accordance with claim 10 wherein each timing signal generator comprises: a first random access memory (RAM) addressed by the received timing data and storing timing control data at each of a plurality of addressable storage locations, said first RAM reading out stored timing control data addressed by said timing data; a second RAM addressed by said format data and storing calibration data at each of a plurality of addressable memory locations, said second RAM reading out stored calibration data addressed by said format data; and means for generating said output timing signal following the start of each test cycle with a delay following said BOC signal pulse determined in accordance with a combination of the timing control data read out of said first RAM, the calibration data read out of said second RAM and said period start data.

Claim 14

An integrated circuit tester in accordance with claim 10 wherein each timing signal generator comprises: a first random access memory (RAM) addressed by said timing data and storing first timing control data at each of a plurality of addressable storage locations, said first RAM reading out stored timing control data when addressed by said timing data, wherein the read out timing control data consists of first and second portions; a second RAM addressed by said format data and storing calibration data at each of a plurality of addressable memory locations, said second RAM reading out stored calibration data addressed by said format data; a counter for generating an output pulse when a number of pulses of said master clock signal occurring since a last BOC signal pulse reaches a limit indicated by said first portion of said timing control data read out of said first RAM; means for logically combining the calibration data read out of said second RAM, the second portion of the timing control data read out of said first RAM, and said period start data generated by said period generator to produce delay control data; and means for delaying the counter output pulse by a time determined by said delay control data thereby to produce said output timing signal.

Claim 15

The integrated circuit tester in accordance with claim 12 further comprising means corresponding to each timing signal generator for receiving the output timing signal produced thereby, for receiving the same format data received by the corresponding timing signal generator, and for implementing a test event referenced by the received format data upon receiving the output timing signal.

Claim 16

The integrated circuit tester in accordance with claim 10 further comprising means corresponding to each timing signal generator for receiving the output timing signal produced thereby, for receiving the same format data received by the corresponding timing signal generator, and for implementing a test event referenced by the received format data upon receiving the output timing signal.

Claim 17

The integrated circuit tester in accordance with claim 8 further comprising means corresponding to each timing signal generator for receiving the output timing signal produced thereby, for receiving the same format data received by the corresponding timing signal generator, and for implementing a test event referenced by the received format data upon receiving the output timing signal.