US5225775A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ic testing device for permitting adjustment of timing of a test signal
Assignee: Advantest Corp
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Filing: 1991-02-01
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Granted: 1993-07-06
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Expires: 2011-02-01
Abstract
Abstract An IC testing device in which the timing for sending out test signals and the timings for acquisition of IC output response signals can be adjusted in accordance with delay times (T 1 to T n ) in transmission lines (L 1 to L n ) of an IC connection board (81) to which terminals (P 1 to P n ) of an IC under test (1) are connected. A nonvolatile storage (83) is provided on the IC connection board (81) and data on the delay times (T 1 to T n ) in the transmission lines (L 1 to L n ) are prestored in the storage. Even if the IC connection board (81) is replaced with another one, the tester main body of the testing device needs only to read out the data from the storage (83) at the start of testing the IC and to adjust the send-out timing and the acquisition timing, based on the read-out data. Thus, the testing time can be reduced. Also, there in no need to identify the individual IC connection boards (81 ).
Inventors
- 👤 Takashi Sekino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:19
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31908; G01R31/3191; G01R31/2801; G01R31/2806; G01R31/2851; G01R31/2882; G01R31/31905; G01R35/00; G01R35/02
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
220 words
An IC testing device for testing an IC under test having a plurality of IC terminals, comprising: a tester main body having a plurality of tester main body terminals and which derives a plurality of test signals of logical levels from a timing signal and a pattern to be applied to said IC under test, provides the test signals to said plurality of tester main body terminals corresponding to said plurality of IC terminals, compares each of a plurality of output response signals acquired from said IC terminals via said tester main body terminals with a reference voltage to determine a logic level of each output response signal, and makes a logical comparison between said logic level and an expected value pattern; and an IC connection board comprising a plurality of transmission lines interconnectably coupling said tester main body terminals and said IC terminals; and a nonvolatile memory for storing delay time data representative of delay times in said transmission lines of said IC connection board corresponding to said terminals of said IC under test; and wherein said tester main body is capable of adjusting timing of said test signals provided to the IC terminals and adjusting acquisition timing of said output response signals acquired from said IC terminals based on said delay time data read from said nonvolatile memory.
Claim 2
Dependent Claim
220 words
An IC testing device for testing an IC under test having a plurality of IC terminals, comprising: a tester main body having a plurality of tester main body terminals and which derives a plurality of test signals of logical levels from a timing signal and a pattern to be applied to said IC under test, provides the test signals to said plurality of tester main body terminals corresponding to said plurality of IC terminals, compares each of a plurality of output response signals acquired from said IC terminals via said tester main body terminals with a reference voltage to determine a logic level of each output response signal, and makes a logical comparison between said logic level and an expected value pattern; and an IC connection board comprising a plurality of transmission lines interconnectably coupling said tester main body terminals and said IC terminals; and a nonvolatile memory for storing delay time data representative of delay times in said transmission lines of said IC connection board corresponding to said terminals of said IC under test; and wherein said tester main body is capable of adjusting timing of said test signals provided to the IC terminals and adjusting acquisition timing of said output response signals acquired from said IC terminals based on said delay time data read from said nonvolatile memory.
Claim 3
Dependent Claim
71 words
The IC testing device of claim 1, wherein said IC connection board further comprises a flag register; and wherein said tester main body comprises control means for reading a state of said flag register when beginning testing of said IC under test and, when said flag register is in a reset state, for effecting control to set said flag register and subsequently read said delay time data from said nonvolatile memory.
Claim 4
Dependent Claim
95 words
The IC testing device of claim 2, wherein said tester main body further comprises a file register; and wherein said control means comprises means for storing in said file register said data read from said nonvolatile memory and, when said flag register is in a set state when beginning testing of said IC under test, for effecting control to adjust the timing of said test signals provided to the IC terminals and adjust the acquisition timing of said output response signals acquired from said IC terminals based on said data stored in said file register.
Claim 5
Dependent Claim
65 words
The IC testing device of claim 3, wherein said tester main body further comprises first skew adjusting circuits for adjusting the timing of said test signals provided to said IC under test; second skew adjusting circuits for adjusting the acquisition timing of said output response signals; and delay amount setting means for setting amounts of delay in said first and second skew adjusting circuits, respectively.
Claim 6
Dependent Claim
95 words
The IC testing device of claim 4, wherein said delay amount setting means comprises: first adjusting data storing means for storing skew adjusting data for said test signals in said tester main body; second adjusting data storing means for storing skew adjusting data for said output response signals in said testing main body; and calculating means for calculating said amounts of delay to be set in said first and second skew adjusting circuits, based on the contents of said first and second adjusting data storing means and said delay time data in said file register.
Claim 7
Dependent Claim
42 words
The IC testing device of claim 3, wherein said control means comprises means for resetting said flag register to be cleared to zero when the power supply thereto is stopped when said IC connection board is disconnected from said tester main body.
Claim 8
Dependent Claim
41 words
The IC testing device of claim 3, wherein said flag register comprises a register having a power-on reset function which is reset when the power supply is connected thereto when said IC connection board is connected to said tester main body.
Claim 9
Dependent Claim
74 words
The IC testing device of claim 3, further comprising a secondary IC connection board provided opposite said IC connection board, said secondary IC connection board comprising a plurality of contact leads connected at one end to said transmission lines and making contact at the other ends of said transmission lines with said IC terminals of said IC under test; and another nonvolatile storage means for storing data on delay times in said contact leads.
Claim 10
Dependent Claim
42 words
The IC testing device of claim 2, wherein said control means comprises means for resetting said flag register to be cleared to zero when the power supply thereto is stopped when said IC connection board is disconnected from said tester main body.
Claim 11
Dependent Claim
41 words
The IC testing device of claim 2, wherein said flag resister comprises a register having a power-on reset function which is reset when the power supply is connected thereto when said IC connection board is connected to said tester main body.
Claim 12
Dependent Claim
72 words
The IC testing device of claim 2, further comprising a secondary IC connection board provided opposite said IC connection board, said secondary IC connection board comprising a plurality of contact leads connected at one end to said transmission lines and making contact at the other ends of said transmission lines with said IC terminals of said under test; and another nonvolatile storage for storing data on delay times in said contact leads.
Claim 13
Dependent Claim
106 words
The IC testing device of claim 11, wherein said second IC connection board further comprises a second flag register; and wherein said control means comprises means for reading from said second flag register when beginning testing of said IC under test and, when in a reset state, for effecting control to set said second flag register, read data from said another nonvolatile storage and then adjust the timing of said test signals and the acquisition timing of said output response signals based on a result of addition of said data read from said another nonvolatile storage and said delay time data read from said nonvolatile memory.
Claim 14
Dependent Claim
147 words
An IC testing device having tester main body terminals for testing an IC under test having IC terminals, comprising: an IC connection board comprising a plurality of transmission lines interconnectably coupling the tester main body terminals and the IC terminals; and nonvolatile storage means for storing delay time data representative of delay times in said transmission lines of said IC connection board; and a tester main body having said tester main body terminals interconnectably coupled to said IC correction board and comprising means for reading the delay time data from said nonvolatile storage means, for providing test signals to the IC terminals via the tester main body terminals with a timing adjusted in accordance with said delay time data, and for acquiring output response signals from the IC terminals via the tester main body terminals with an acquisition timing adjusted in accordance with the delay time data.
Claim 15
Dependent Claim
147 words
An IC testing device having tester main body terminals for testing an IC under test having IC terminals, comprising: an IC connection board comprising a plurality of transmission lines interconnectably coupling the tester main body terminals and the IC terminals; and nonvolatile storage means for storing delay time data representative of delay times in said transmission lines of said IC connection board; and a tester main body having said tester main body terminals interconnectably coupled to said IC correction board and comprising means for reading the delay time data from said nonvolatile storage means, for providing test signals to the IC terminals via the tester main body terminals with a timing adjusted in accordance with said delay time data, and for acquiring output response signals from the IC terminals via the tester main body terminals with an acquisition timing adjusted in accordance with the delay time data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-07-05 | 1997-01-04 | 1997-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-07-05 | 2001-01-04 | 2001-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-07-05 | 2005-01-04 | 2005-07-06 | $7700.00 | Window Closed / Lapsed |