Integrated circuit tester having multiple period generators

Claim 2

A tester for carrying out test activities at each terminal of an integrated circuit device under test (DUT), the test being organized into successive main test cycles, each main test cycle spanning a plurality of auxiliary test cycles, the tester comprising: a main period generator for generating main test cycle data indicating a beginning time of each main test cycle signal; an auxiliary period generator for generating auxiliary test cycle data indicating a beginning time of each auxiliary test cycle; a pattern generator for generating a plurality of timeset data values for each main test cycle; and a plurality of tester channels, each tester channel for receiving the main and auxiliary test cycle data, each tester channel for receiving a separate one of said timeset values, each tester channel for receiving separate input selection control data selectively controlling whether the tester channel responds to said main test cycle data or to said auxiliary test cycle data, each tester channel, when responding to main test cycle data received at the beginning of a main test cycle, for carrying out a test activity at one of said DUT terminals once during said main test cycle, the test activity being timed in accordance with a combination of the received main test cycle data and the received timeset data, and wherein each tester channel, when responding to the auxiliary test cycle data received at the beginning of a main test cycle, for carrying out a test activity at one of said DUT terminals once during each of a plurality of auxiliary test cycles spanned by said main test cycle, the test activity being timed in accordance with a combination of the received auxiliary test cycle data and the received timeset data.

Claim 3

The tester in accordance with claim 1 wherein said pattern generator also generates period set data at the beginning of each main test cycle, the period set data indicating a length of the main test cycle, said main period generator determining therefrom the beginning time for a next main test cycle.

Claim 4

The tester in accordance with claim 1 wherein said period set data also indicates a length of each auxiliary cycle occurring during a next main test cycle, said auxiliary period generator determining therefrom a beginning time for each auxiliary test cycle spanned by a next main test cycle.

Claim 5

The tester in accordance with claim 1 wherein the main period generator comprises: a first random access memory addressed by said period set data and reading out main period length data in response thereto, and means responsive to said main period length data for generating said main test cycle data.

Claim 6

The tester in accordance with claim 4 wherein the auxiliary period generator comprises: a second random access memory addressed by said period set data and reading out auxiliary period length data in response thereto, and means responsive to said auxiliary period length data for generating said auxiliary test cycle data.

Claim 7

A tester for carrying out test activities at each terminal of an integrated circuit device under test (DUT) during successive main test cycles, each main test cycle spanning a plurality of auxiliary test cycles, the tester comprising: a main period generator for generating main test cycle data indicating a beginning time of each main test cycle signal; a plurality of auxiliary period generators, each for generating separate auxiliary test cycle data indicating a beginning time of an auxiliary test cycle, a pattern generator for generating a plurality of timeset data values for each main test cycle; and a plurality of tester channels, each tester channel for receiving the main test cycle data and for receiving the auxiliary test cycle data produced by each auxiliary period generator, each tester channel for receiving a separate one of said timeset values, each tester channel also for receiving separate input selection control data selectively controlling whether the tester channel responds to said main test cycle data or to auxiliary test cycle data from one of said auxiliary period generators, each tester channel, when responding to main test cycle data received at the beginning of a main test cycle, carrying out a test activity at one of said DUT terminals once during said main test cycle, the test activity being timed in accordance with a combination of the received main test cycle data and the received timeset data, and each tester channel, when responding to auxiliary test cycle data received at the beginning of a main test cycle, carrying out a test activity at one of said DUT terminals once during each auxiliary test cycle spanned by said main test cycle, the test activity being timed in accordance with a combination of received auxiliary test cycle data from one of said auxiliary period generators and the received timeset data.

Claim 8

A tester for carrying out test activities at each terminal of an integrated circuit device under test (DUT) during successive main test cycles, each main test cycle spanning a plurality of auxiliary test cycles, the tester comprising: a main period generator for generating main test cycle data indicating a beginning time of each main test cycle signal; a plurality of auxiliary period generators, each for generating separate auxiliary test cycle data indicating a beginning time of an auxiliary test cycle, a pattern generator for generating a plurality of timeset data values for each main test cycle; and a plurality of tester channels, each tester channel for receiving the main test cycle data and for receiving the auxiliary test cycle data produced by each auxiliary period generator, each tester channel for receiving a separate one of said timeset values, each tester channel also for receiving separate input selection control data selectively controlling whether the tester channel responds to said main test cycle data or to auxiliary test cycle data from one of said auxiliary period generators, each tester channel, when responding to main test cycle data received at the beginning of a main test cycle, carrying out a test activity at one of said DUT terminals once during said main test cycle, the test activity being timed in accordance with a combination of the received main test cycle data and the received timeset data, and each tester channel, when responding to auxiliary test cycle data received at the beginning of a main test cycle, carrying out a test activity at one of said DUT terminals once during each auxiliary test cycle spanned by said main test cycle, the test activity being timed in accordance with a combination of received auxiliary test cycle data from one of said auxiliary period generators and the received timeset data.

Claim 9

The tester in accordance with claim 6 wherein said pattern generator also generates period set data at the beginning of each main test cycle, the period set data indicating a length of the main test cycle, said main period generator determining therefrom the beginning time for a next main test cycle.

Claim 10

The tester in accordance with claim 6 wherein said period set data also indicates a length of each auxiliary cycle occurring during a next main test cycle, said auxiliary period generator determining therefrom a beginning time for each auxiliary test cycle spanned by a next main test cycle.

Claim 11

The tester in accordance with claim 6 wherein the main period generator comprises: a first random access memory addressed by said period set data and reading out main period length data in response thereto, and means responsive to said main period length data for generating said main test cycle data.

Claim 12

The tester in accordance with claim 9 wherein each auxiliary period generator comprises: a second random access memory addressed by said period set data and reading out auxiliary period length data in response thereto, and means responsive to said auxiliary period length data for generating said auxiliary test cycle data.

Claim 13

A tester for carrying out test activities at each terminal of an integrated circuit device under test (DUT) during successive main test cycles, each main test cycle spanning a plurality of auxiliary test cycles, the tester comprising: a main period generator for generating main test cycle data indicating a beginning time of each main test cycle signal; a pattern generator for generating a plurality of timeset data values for each main test cycle; and a plurality of tester channels, each tester channel receiving the main test cycle data produced by the main period generator, each tester channel generating auxiliary test cycle data for each main test cycle, the auxiliary test cycle data indicating a beginning time of each auxiliary test cycle spanned by the main test cycle, each tester channel receiving a separate one of said timeset values, each tester channel also receiving separate input selection control data selectively controlling whether the tester channel responds to said main test cycle data or to its generated auxiliary test cycle data, each tester channel, when responding to main test cycle data received at the beginning of a main test cycle, carrying out a test activity at one of said DUT terminals once during said main test cycle, the test activity being timed in accordance with a combination of the received main test cycle data and the received timeset data, and each tester channel, when responding to its generated auxiliary test cycle data, carrying out a test activity at one of said DUT terminals once during each auxiliary test cycle spanned by a main test cycle, the test activity being timed in accordance with a combination of auxiliary test cycle data the received timeset data.

Claim 14

A tester for carrying out test activities at each terminal of an integrated circuit device under test (DUT) during successive main test cycles, each main test cycle spanning a plurality of auxiliary test cycles, the tester comprising: a main period generator for generating main test cycle data indicating a beginning time of each main test cycle signal; a pattern generator for generating a plurality of timeset data values for each main test cycle; and a plurality of tester channels, each tester channel receiving the main test cycle data produced by the main period generator, each tester channel generating auxiliary test cycle data for each main test cycle, the auxiliary test cycle data indicating a beginning time of each auxiliary test cycle spanned by the main test cycle, each tester channel receiving a separate one of said timeset values, each tester channel also receiving separate input selection control data selectively controlling whether the tester channel responds to said main test cycle data or to its generated auxiliary test cycle data, each tester channel, when responding to main test cycle data received at the beginning of a main test cycle, carrying out a test activity at one of said DUT terminals once during said main test cycle, the test activity being timed in accordance with a combination of the received main test cycle data and the received timeset data, and each tester channel, when responding to its generated auxiliary test cycle data, carrying out a test activity at one of said DUT terminals once during each auxiliary test cycle spanned by a main test cycle, the test activity being timed in accordance with a combination of auxiliary test cycle data the received timeset data.

Claim 15

The tester in accordance with claim 11 wherein said pattern generator also generates period set data at the beginning of each main test cycle, the period set data indicating a length of the main test cycle, said main period generator determining therefrom the beginning time for a next main test cycle.

Claim 16

The tester in accordance with claim 6 wherein said period set data also indicates a length of each auxiliary cycle occurring during a next main test cycle, said auxiliary period generator determining therefrom a beginning time for each auxiliary test cycle spanned by a next main test cycle.

Claim 17

The tester in accordance with claim 11 wherein the main period generator comprises: a first random access memory addressed by said period set data and reading out main period length data in response thereto, and means responsive to said main period length data for generating said main test cycle data.

Claim 18

The tester in accordance with claim 14 wherein said auxiliary period generator comprises: a second random access memory addressed by said period set data and reading out auxiliary period length data in response thereto, and means responsive to said auxiliary period length data for generating said auxiliary test cycle data.