Patent US3488706A successfully refreshed from Google Patents.
Patent US6060778A successfully refreshed from Google Patents.
US6060778A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ball grid array package
Assignee: Mosaid Technologies Inc
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Filing: 1998-04-15
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Granted: 2000-05-09
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Expires: 2018-04-15
Abstract
Abstract Disclosed is a packaged integrated circuit device with high heat dissipation performance and low weight. The packaged integrated circuit device includes an interconnection substrate having at least one layer of conductive trace material and at least one layer of insulating material and also having a first surface and a second surface disposed opposite to the first surface and having a plurality of electrical contacts formed on the second surface. At least one metal thermal conductive layer having a first surface is attached on the first surface of the interconnection substrate and having a second surface exposed to an exterior. A through hole region is formed in the interconnection substrate and the thermal conductive layer. An integrated circuit chip having a first surface exposed to an exterior and having also a second surface with a plurality of bond pads, opposite to the first surface of the integrated circuit chip, is placed within the through hole region. A plurality of bond wires make an electrical connection of the bond pads with the conductive trace layers. The bond wires and the integrated circuit chip are enclosed with an insulating encapsulant material. The through hole region is also filled with the insulating encapsulant material.
Inventors
- 👤 Tae Sung Jeong
- 👤 Ki Tae Ryu
- 👤 Tae Keun Lee
- 👤 Keun Hyoung Choi
- 👤 Han Shin Youn
- 👤 Jum Sook Park
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:22
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W74/117; H10W40/00; H10W40/10; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/681; H10W70/682; H10W70/685; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/541; H10W72/547; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/874; H10W72/884; H10W74/131; H10W74/142; H10W90/00; H10W90/701; H10W90/731; H10W90/734; H10W90/736; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
238 words
A packaged integrated circuit device, comprising: an interconnection substrate having at least one conductive trace layer and at least one insulating layer and also having a first surface and a second surface having a plurality of electrical contacts thereon, opposite to the first surface of the interconnection substrate; a dielectric layer attached to an outer portion of the first surface of the interconnection substrate; a metal thermal conductive layer having a first surface and a second surface opposite to the first surface thereof, the first surface of the metal thermal conductive layer being attached to an internal portion of the first surface of the interconnection substrate and also being in contact with the internal end portion of the dielectric layer; a hole region which is formed at the central portion of the interconnection substrate and which exposes the first surface of the metal thermal conductive layer; an integrated circuit chip disposed within the hole region, the integrated circuit chip having a first surface attached the first surface of the interconnection substrate and a second surface opposite to the first surface of the integrated circuit chip, the second surface of the integrated circuit chip having a plurality of bonding pads formed thereon; a plurality of bond wires for electrically connecting the bond pads with the conductive trace layer; and an encapsulant material enclosing bond wires and the integrated circuit chip, the hole region being filled with the encapsulant material.
Claim 2
Dependent Claim
238 words
A packaged integrated circuit device, comprising: an interconnection substrate having at least one conductive trace layer and at least one insulating layer and also having a first surface and a second surface having a plurality of electrical contacts thereon, opposite to the first surface of the interconnection substrate; a dielectric layer attached to an outer portion of the first surface of the interconnection substrate; a metal thermal conductive layer having a first surface and a second surface opposite to the first surface thereof, the first surface of the metal thermal conductive layer being attached to an internal portion of the first surface of the interconnection substrate and also being in contact with the internal end portion of the dielectric layer; a hole region which is formed at the central portion of the interconnection substrate and which exposes the first surface of the metal thermal conductive layer; an integrated circuit chip disposed within the hole region, the integrated circuit chip having a first surface attached the first surface of the interconnection substrate and a second surface opposite to the first surface of the integrated circuit chip, the second surface of the integrated circuit chip having a plurality of bonding pads formed thereon; a plurality of bond wires for electrically connecting the bond pads with the conductive trace layer; and an encapsulant material enclosing bond wires and the integrated circuit chip, the hole region being filled with the encapsulant material.
Claim 3
Dependent Claim
69 words
The packaged integrated circuit device of claim 1, wherein, the integrated circuit chip is aligned and held within the hole region by a sucking force of vacuum acting on the first surface thereof, and the plurality of bond pads on the integrated circuit chip and the conductive trace layer are electrically connected to each other by the plurality of bond wires in a condition where the sucking force acts.
Claim 4
Dependent Claim
28 words
The packaged integrated circuit device of claim 1, wherein the thermal conductive foil is made of a material selected from the group consisting of copper, aluminum, and silver.
Claim 5
Dependent Claim
17 words
The packaged integrated circuit device of claim 1, wherein the conductive trace layer is made of copper.
Claim 6
Dependent Claim
28 words
The packaged integrated circuit device of claim 1, the hole region has a circular cross sectional shape and includes at least one ear portion of a circular shape.
Claim 7
Dependent Claim
17 words
The packaged integrated circuit device of claim 1, wherein the plurality of electrical contacts are solder balls.
Claim 8
Dependent Claim
28 words
The packaged integrated circuit device of claim 1, wherein the integrated circuit chip is attached to the metal thermal conductive metal layer by an adhesive material containing silver.
Claim 9
Dependent Claim
28 words
The packaged integrated circuit device of claim 1, wherein the dielectric layer is made of a material selected from a group consisting of solder resist, polyimide, and epoxy.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-09 | 2003-11-08 | 2004-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-09 | 2007-11-08 | 2008-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-09 | 2011-11-08 | 2012-05-09 | $7700.00 | Window Closed / Lapsed |