US6060406A
Expired / Lapsed
US
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MOS transistors with improved gate dielectrics
Assignee: Nokia of America Corp
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Filing: 1998-05-28
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Granted: 2000-05-09
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Expires: 2018-05-28
Abstract
Abstract The specification describes silicon MOS devices with gate dielectrics having the composition Ta 1-x Al x O y , where x is 0.03-0.7 and y is 1.5-3, Ta 1-x Si x O y , where x is 0.05-0.15, and y is 1.5-3, and Ta 1-x-z Al x Si z O y , where 0.7>x+z>0.05, z<0.15 and y is 1.5-3. By comparison with the standard SiO 2 gate dielectric material, these materials provide improved dielectric properties and also remain essentially amorphous to high temperatures. This retards formation of SiO 2 interfacial layers which otherwise dominate the gate dielectric properties and reduce the overall effectiveness of using a high dielectric material.
Inventors
- 👤 Glen B. Alers
- 👤 Robert McLemore Fleming
- 👤 Lynn Frances Schneemeyer
- 👤 Robert Bruce van Dover
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:16
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10P; H10P10/00; H10D64/01342; H10D64/01352; H10D64/60; H10D64/66; H10D64/68; H10D64/691; H10P14/00; H10P14/60; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6329; H10P14/6334; H10P14/69; H10P14/692; H10P14/6921; H10P14/6928; H10P14/6931; H10P14/6938; H10P14/6939; H10P14/69391; H10P14/69393; H10P14/69397; H10D64/667; H10D64/668; H10D64/681; H10D64/685
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
97 words
Method for the manufacture of an MOS silicon device comprising the steps of: a. forming a dielectric layer on a silicon substrate, b. forming a gate electrode on said dielectric layer, the invention characterized in the dielectric layer has a composition selected from the group consisting of: (1) Ta 1-x Al x O y , where x is 0.03-0.7 and y is 1.5-3, (2) Ta 1-x Si x O y , where x is 0.05-0.15, and y is 1.5-3, and (3) Ta 1-x-z Al x Si z O y , where 0.7>x+z>0.05, z<0.15 and y is 1.5-3.
Claim 2
Dependent Claim
97 words
Method for the manufacture of an MOS silicon device comprising the steps of: a. forming a dielectric layer on a silicon substrate, b. forming a gate electrode on said dielectric layer, the invention characterized in the dielectric layer has a composition selected from the group consisting of: (1) Ta 1-x Al x O y , where x is 0.03-0.7 and y is 1.5-3, (2) Ta 1-x Si x O y , where x is 0.05-0.15, and y is 1.5-3, and (3) Ta 1-x-z Al x Si z O y , where 0.7>x+z>0.05, z<0.15 and y is 1.5-3.
Claim 3
Dependent Claim
24 words
The method of claim 1 in which the dielectric layer has a composition Ta 1- Al x O y , where x is 0.05-0.4.
Claim 4
Dependent Claim
17 words
The method of claim 1 wherein the dielectric layer has a thickness in the range 20-100 Angstroms.
Claim 5
Dependent Claim
11 words
The method of claim 1 wherein the gate electrode is polysilicon.
Claim 6
Dependent Claim
22 words
The method of claim 1 wherein the gate electrode is a material selected from the group consisting of TiN, WN and WSi.
Claim 7
Dependent Claim
146 words
Method for the manufacture of an MOS silicon device with an MOS gate and source and drain regions comprising the steps of: a. forming a dielectric layer on a silicon substrate, b. forming a gate electrode layer on said dielectric layer, c. patterning said gate electrode layer to define the MOS gate electrode, d. implanting source and drain regions using said MOS gate electrode as a mask, e. heating the silicon substrate to a temperature of at least 850° C., the invention characterized in the dielectric layer has a composition selected from the group consisting of: (1) Ta 1-x Al x O y , where x is 0.03-0.7 and y is 1.5-3, (2) Ta 1-x Si x O y , where x is 0.05-0.15, and y is 1.5-3, and (3) Ta 1-x-z Al x Si x O y , where 0.7>x+z>0.05, z<0.15 and y is 1.5-3.
Claim 8
Dependent Claim
146 words
Method for the manufacture of an MOS silicon device with an MOS gate and source and drain regions comprising the steps of: a. forming a dielectric layer on a silicon substrate, b. forming a gate electrode layer on said dielectric layer, c. patterning said gate electrode layer to define the MOS gate electrode, d. implanting source and drain regions using said MOS gate electrode as a mask, e. heating the silicon substrate to a temperature of at least 850° C., the invention characterized in the dielectric layer has a composition selected from the group consisting of: (1) Ta 1-x Al x O y , where x is 0.03-0.7 and y is 1.5-3, (2) Ta 1-x Si x O y , where x is 0.05-0.15, and y is 1.5-3, and (3) Ta 1-x-z Al x Si x O y , where 0.7>x+z>0.05, z<0.15 and y is 1.5-3.
Claim 9
Dependent Claim
23 words
The method of claim 6 in which the dielectric layer has a composition Ta 1-x Al x O y where x is 0.05-0.4.
Claim 10
Dependent Claim
17 words
The method of claim 6 wherein the dielectric layer has a thickness in the range 20-100 Angstroms.
Claim 11
Dependent Claim
11 words
The method of claim 6 wherein the gate electrode is polysilicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-09 | 2003-11-08 | 2004-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-09 | 2007-11-08 | 2008-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-09 | 2011-11-08 | 2012-05-09 | $7700.00 | Window Closed / Lapsed |