Patent US6055656A successfully refreshed from Google Patents.
US6055656A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Control register bus access through a standardized test access port
Assignee: Intel Corp
•
Filing: 1995-05-02
•
Granted: 2000-04-25
•
Expires: 2015-05-02
Abstract
Abstract A scheme for accessing a control register bus and control registers of a microprocessor through a test access port which is configured to an established testing standard. A test access port (TAP) of a microprocessor is configured to communicate serially based on a technique specified in the IEEE 1149.1 standard. External serial instructions are converted for parallel transfer to provide control signals for accessing the internal structures. Serial address and data signals are also converted for parallel transfer to access internal structures on a control register bus and parallel outputs are converted to serial format for external output. By permitting external access to low level internal bus architecture, system testing and debug can be performed by utilizing external programming.
Inventors
- 👤 James A. Wilson, Jr.
- 👤 Anthony C. Miller
- 👤 Michael W. Rhodehamel
- 👤 Adrian Carbine
- 👤 Derek B. I. Feltham
- 👤 Sumeet Agrawal
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:36
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318572
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
180 words
A microprocessor providing external diagnostic access comprising: a plurality of control registers; an internal bus coupled to said control registers; a test access port (TAP) configured to receive external programming signals in a serial format; said TAP including a first register that receives a first instruction command in said serial format and converts said first instruction command to a parallel format; a control register unit that receives, in said serial format, an address to one of said control registers for data access thereto, said control register unit being coupled to said TAP and said internal bus; said control register unit including a second register that converts data received in said serial format to said parallel format; in a write operation, said control register unit causing data to be transferred from said second register to said one of said control registers specified by said address responsive to said first instruction command; in a read operation, said control register unit causing data to be transferred from said one of said control registers to said second register responsive to said first instruction command.
Claim 2
Dependent Claim
180 words
A microprocessor providing external diagnostic access comprising: a plurality of control registers; an internal bus coupled to said control registers; a test access port (TAP) configured to receive external programming signals in a serial format; said TAP including a first register that receives a first instruction command in said serial format and converts said first instruction command to a parallel format; a control register unit that receives, in said serial format, an address to one of said control registers for data access thereto, said control register unit being coupled to said TAP and said internal bus; said control register unit including a second register that converts data received in said serial format to said parallel format; in a write operation, said control register unit causing data to be transferred from said second register to said one of said control registers specified by said address responsive to said first instruction command; in a read operation, said control register unit causing data to be transferred from said one of said control registers to said second register responsive to said first instruction command.
Claim 3
Dependent Claim
38 words
The microprocessor of claim 1 wherein said control register unit further includes a bus access logic unit that arbitrates for said internal bus to enable data transfer between said second register and said one of said control registers.
Claim 4
Dependent Claim
33 words
The microprocessor of claim 2 wherein said TAP further includes a decode and control logic unit that decodes said first instruction command and that generates a control signal to said control register unit.
Claim 5
Dependent Claim
32 words
The microprocessor of claim 3 wherein said TAP further includes a finite state controller that generates test access port control signals to said first register and said decode and control logic unit.
Claim 6
Dependent Claim
17 words
The microprocessor of claim 4 wherein said internal bus comprises a data bus and an address bus.
Claim 7
Dependent Claim
18 words
The microprocessor of claim 5 wherein said TAP is configured to operate in accordance with a signaling protocol.
Claim 8
Dependent Claim
165 words
In a microprocessor having a plurality of control registers coupled to an internal bus, and a test access port (TAP), a method of providing external, diagnostic access to said control registers comprising the steps of: receiving external programming signals in a serial format at said test access port; coupling an instruction command in said serial format to a first shift register in said TAP; converting said instruction command to a parallel format; generating a control signal based on said instruction command; coupling serial information which includes an address, for accessing one of said control registers, to a second shift register of a control register unit for data transfer to or from said one of said control registers; converting said serial information to said parallel format; executing a write or read operation to access an addressed control register for data transfer; converting read data to said serial format for output if said data transfer is from one of said control registers to said second shift register.
Claim 9
Dependent Claim
165 words
In a microprocessor having a plurality of control registers coupled to an internal bus, and a test access port (TAP), a method of providing external, diagnostic access to said control registers comprising the steps of: receiving external programming signals in a serial format at said test access port; coupling an instruction command in said serial format to a first shift register in said TAP; converting said instruction command to a parallel format; generating a control signal based on said instruction command; coupling serial information which includes an address, for accessing one of said control registers, to a second shift register of a control register unit for data transfer to or from said one of said control registers; converting said serial information to said parallel format; executing a write or read operation to access an addressed control register for data transfer; converting read data to said serial format for output if said data transfer is from one of said control registers to said second shift register.
Claim 10
Dependent Claim
33 words
The method of claim 7 further including the step of arbitrating for access of said internal bus prior to executing said write or read operation, wherein said access takes priority over microcode execution.
Claim 11
Dependent Claim
27 words
The method of claim 8 wherein said step of coupling serial information also conveys information identifying if a particular access is a read or a write operation.
Claim 12
Dependent Claim
25 words
The method of claim 9 wherein said step of configuring said TAP also includes configuring said TAP to operate in accordance with a signaling protocol.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-04-25 | 2003-10-25 | 2004-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-04-25 | 2007-10-25 | 2008-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-04-25 | 2011-10-25 | 2012-04-25 | $7700.00 | Window Closed / Lapsed |