Efficient data transfer mechanism for input/output devices

Claim 2

In a computer system having a processor, a memory and a system bus for connecting an input/output (I/O) device through a single channel I/O adapter to said memory and processor, a method for transferring data between non-contiguous buffers in the memory and the single channel I/O adapter comprising the steps: defining with a device driver a descriptor queue (DQ) in the memory having a base address (DescrBase) and an n descriptor capacity (DescrCount); at initialization using said device driver to store in the I/O device the DescrBase, the DescrCount and a third value DescrCurrent which at initialization equals the value of the DescrBase; building with the device driver one or more descriptors in the DQ, each corresponding to a different one of the data buffers, said descriptors including at least the starting address of the buffer and a byte count; adding the number of descriptors built to a descriptor enqueue (DescrEnq) value maintained at the I/O device; using a state machine to examine the DescrEnq value for a non-zero condition and fetching with said state machine a number of descriptors from the DQ corresponding to the DescrEnq value starting at the address specified by the DescrCurrent value and incrementing the DescrCurrent value and decrementing the DescrEnq value each time a descriptor is fetched; and using the state machine to read in memory and to transfer across the system bus the buffers specified by the fetched descriptors.

Claim 3

In a computer system having a processor, a memory and a system bus for connecting an input/output (I/O) device to said memory and processor, a method for transferring data between non-contiguous buffers in the memory and the I/O device comprising the steps: defining a descriptor queue (DQ) in the memory having a base address (DescrBase) and an n descriptor capacity (DescrCount); at initialization storing in the I/O device the DescrBase and the DescrCount and storing a third value DescrCurrent which at initialization equals the value of the DescrBase; effecting transfer of data stored in one or more buffers in the memory to the I/O device by; building one or more descriptors in the DQ, each corresponding to a different one of the data buffers, said descriptors including at least the starting address of the buffer and a byte count, adding the number of descriptors built since last added to a descriptor enqueue (DescrEnq) value maintained at the I/O device; at the I/O device using a state machine to examine the DescrEnq value for a non-zero condition and fetching a number of descriptors from the DQ corresponding to the DescrEnq value starting at the address specified by the DescrCurrent value and incrementing the DescrCurrent value each time a descriptor is fetched and decrementing the DescrEnq value each time a descriptor is fetched; and using the state machine to read in memory and transferring across the system bus the buffers specified by the fetched descriptors.

Claim 4

In a computer system having a processor, a memory and a system bus for connecting an input/output (I/O) device to said memory and processor, a method for transferring data between non-contiguous buffers in the memory and the I/O device comprising the steps: defining a descriptor queue (DQ) in the memory having a base address (DescrBase) and an n descriptor capacity (DescrCount); at initialization storing in the I/O device the DescrBase and the DescrCount and storing a third value DescrCurrent which at initialization equals the value of the DescrBase; effecting transfer of data stored in one or more buffers in the memory to the I/O device by; building one or more descriptors in the DQ, each corresponding to a different one of the data buffers, said descriptors including at least the starting address of the buffer and a byte count, adding the number of descriptors built since last added to a descriptor enqueue (DescrEnq) value maintained at the I/O device; at the I/O device using a state machine to examine the DescrEnq value for a non-zero condition and fetching a number of descriptors from the DQ corresponding to the DescrEnq value starting at the address specified by the DescrCurrent value and incrementing the DescrCurrent value each time a descriptor is fetched and decrementing the DescrEnq value each time a descriptor is fetched; and using the state machine to read in memory and transferring across the system bus the buffers specified by the fetched descriptors.

Claim 5

In a computer system having a processor, a memory and a system bus for connecting an input/output (I/O) device to said memory and processor, a method for transferring data between an I/O device and non-contiguous buffers in the memory comprising the steps: defining a descriptor queue (DQ) in the memory having a base address (DescrBase) and an n descriptor capacity (DescrCount); at initialization storing in the I/O device the DescrBase, the DescrCount and storing a third value DescrCurrent which at initialization equals the value of the DescrBase; building a number of descriptors in the DQ and loading a descriptor enqueue (DescrEnq) value at the I/O device indicating the number of descriptors built and available; examining by a state machine the DescrEnq value for a non-zero condition and fetching by the state machine during said non-zero condition descriptors as required from the DQ starting at the address specified by the DescrCurrent value and incrementing the DescrCurrent value and decrementing the DescrEnq value each time a descriptor is fetched; and transferring by the state machine across the system bus received data for storage in the buffers specified by the fetched descriptors.

Claim 6

In a computer system having a processor, a memory and a system bus for connecting an input/output (I/O) device to said memory and processor, a method for transferring data between an I/O device and non-contiguous buffers in the memory comprising the steps: defining a descriptor queue (DQ) in the memory having a base address (DescrBase) and an n descriptor capacity (DescrCount); at initialization storing in the I/O device the DescrBase, the DescrCount and storing a third value DescrCurrent which at initialization equals the value of the DescrBase; building a number of descriptors in the DQ and loading a descriptor enqueue (DescrEnq) value at the I/O device indicating the number of descriptors built and available; examining by a state machine the DescrEnq value for a non-zero condition and fetching by the state machine during said non-zero condition descriptors as required from the DQ starting at the address specified by the DescrCurrent value and incrementing the DescrCurrent value and decrementing the DescrEnq value each time a descriptor is fetched; and transferring by the state machine across the system bus received data for storage in the buffers specified by the fetched descriptors.

Claim 7

In a computer system having a processor including an input/output (I/O) device driver, a memory, host bridge logic and a system bus for connecting an (I/O) device to said memory and processor via said host bridge logic, a method for transferring data between non-contiguous buffers in the memory and the I/O device comprising the steps: defining a descriptor queue (DQ) in the memory having a base address (DescrBase) and an n descriptor capacity (DescrCount); at initialization storing in the I/O device the DescrBase and the DescrCount and storing a third value DescrCurrent which at initialization equals the value of the DescrBase; building a number of descriptors in the DQ, each corresponding to a different one of the data buffers, said descriptors including at least the starting address of the buffer and a byte count and loading a descriptor enqueue (DescrEnq) value at the I/O device indicating the number of descriptors built and available; at the I/O device using a state machine to examine the DescrEnq value for a non-zero condition and fetching during said non-zero condition descriptors as required from the DQ starting at the address specified by the DescrCurrent value and incrementing the DescrCurrent value and decrementing the DescrEnq value each time a descriptor is fetched; and using the state machine to transfer across the system bus received data for storage in the buffers specified by the fetched descriptors.

Claim 8

In a computer system having a processor including an input/output (I/O) device driver, a memory, host bridge logic and a system bus for connecting an (I/O) device to said memory and processor via said host bridge logic, a method for transferring data between non-contiguous buffers in the memory and the I/O device comprising the steps: defining a descriptor queue (DQ) in the memory having a base address (DescrBase) and an n descriptor capacity (DescrCount); at initialization storing in the I/O device the DescrBase and the DescrCount and storing a third value DescrCurrent which at initialization equals the value of the DescrBase; building a number of descriptors in the DQ, each corresponding to a different one of the data buffers, said descriptors including at least the starting address of the buffer and a byte count and loading a descriptor enqueue (DescrEnq) value at the I/O device indicating the number of descriptors built and available; at the I/O device using a state machine to examine the DescrEnq value for a non-zero condition and fetching during said non-zero condition descriptors as required from the DQ starting at the address specified by the DescrCurrent value and incrementing the DescrCurrent value and decrementing the DescrEnq value each time a descriptor is fetched; and using the state machine to transfer across the system bus received data for storage in the buffers specified by the fetched descriptors.

Claim 12

The device driver of claim 6 further including a fifth code module that processes data in said data buffer if the predetermined condition includes a non-zero integer.

Claim 13

The device driver of claim 7 wherein the fifth code module returns the data buffers, from which data as been processed, to a free buffer pool.

Claim 14

The device driver of claim 6 further including a sixth code module that resets the non-zero integer to zero after the data in said data buffer has been processed.

Claim 15

The device driver of claim 9 further including a seventh code module that increments a printer associated with the status queue from a last process position to a current position whereat processing is to begin.

Claim 16

A controller for transferring data between a host system and external devices that are connected to the network controller the host system having memory with data buffers, a descriptor queue and a receive status queue, the controller comprising: a first register that maintains a number of descriptors that are currently available in the descriptor queue for use in a direct memory access (DMA) transfer; a second register that maintains an address of the location of the first descriptor of the currently available descriptors in the descriptor queue; a buffer for temporarily storing currently available descriptors that are obtained from the descriptor queue; and hardware circuitry that controls obtaining the currently available descriptors from the descriptor queue for temporary storage in the descriptor FIFO, the circuitry retrieving as many currently available descriptors as possible to fill the descriptor FIFO, based on the number in the first register and the address in the second register.

Claim 17

A controller for transferring data between a host system and external devices that are connected to the network controller the host system having memory with data buffers, a descriptor queue and a receive status queue, the controller comprising: a first register that maintains a number of descriptors that are currently available in the descriptor queue for use in a direct memory access (DMA) transfer; a second register that maintains an address of the location of the first descriptor of the currently available descriptors in the descriptor queue; a buffer for temporarily storing currently available descriptors that are obtained from the descriptor queue; and hardware circuitry that controls obtaining the currently available descriptors from the descriptor queue for temporary storage in the descriptor FIFO, the circuitry retrieving as many currently available descriptors as possible to fill the descriptor FIFO, based on the number in the first register and the address in the second register.

Claim 18

The controller of claim 11 wherein the hardware circuitry includes a state machine.

Claim 19

The controller of claim 12 wherein the state machine decrements the number of said first register by a value equal to the number of descriptors removed from said descriptor queue by the state machine.

Claim 20

A network interface card comprising: a single channel operatively coupling said card to at least one device; a first register that holds a base address whereat a descriptor queue is located in a memory; a second register that holds a count indicating the number of entries in the descriptor queue; a storage that stores descriptors transferred from the descriptor queue; and a state machine that controls transferring currently available descriptors from the descriptor queue for temporary storage in the storage wherein the number of descriptors transferred is based upon the number in the second register and the address in the first register.

Claim 21

A network interface card comprising: a single channel operatively coupling said card to at least one device; a first register that holds a base address whereat a descriptor queue is located in a memory; a second register that holds a count indicating the number of entries in the descriptor queue; a storage that stores descriptors transferred from the descriptor queue; and a state machine that controls transferring currently available descriptors from the descriptor queue for temporary storage in the storage wherein the number of descriptors transferred is based upon the number in the second register and the address in the first register.

Claim 22

The controller of claim 11 or the network interface card of claim 14 further including a third register that holds an address indicating the current position in the queue whereat processing is being done.

Claim 23

The controller of claim 11 or the network interface card of claim 14 further including: a status base register that holds a base address whereat a status queue is located in memory; a status count register that holds a count representative of the number of entries in the status queue; and a status current register holding an address indicating a current position in said status register whereat processing is being done.

Claim 24

A host system comprising: a memory; a plurality of data buffers that store data distributed throughout said memory; a device driver that generates a descriptor queue containing entries identifying locations of data buffer and actions to be taken relative to data in said buffers; and a status queue that holds information regarding actions done to data in said registers wherein said device driver monitors the status queue and return buffers to a free buffer pool based upon a predetermined condition detected at said status queue.

Claim 25

A host system comprising: a memory; a plurality of data buffers that store data distributed throughout said memory; a device driver that generates a descriptor queue containing entries identifying locations of data buffer and actions to be taken relative to data in said buffers; and a status queue that holds information regarding actions done to data in said registers wherein said device driver monitors the status queue and return buffers to a free buffer pool based upon a predetermined condition detected at said status queue.

Claim 26

A data transfer mechanism for use in a computer comprising: a memory; a descriptor queue position in said memory; a device driver that generates and loads entries in said descriptor queue, said entries at least indicating locations whereat data buffers are located in the memory; a single channel adapter; a bus operatively coupling the single channel adapter to the memory; a descriptor base address register positioned in the adapter; a descriptor count register positioned in the adapter; a descriptor current address register positioned in the adapter; a descriptor enqueue register positioned in the adapter wherein each of the registers is loaded with control information by said device driver at an initialization period; a memory, in said adapter, that temporarily stores descriptors; and a state machine that accesses selected ones of the registers and transfer descriptors from the descriptor queue to the memory based upon information contained in said selected ones of the registers.

Claim 27

A data transfer mechanism for use in a computer comprising: a memory; a descriptor queue position in said memory; a device driver that generates and loads entries in said descriptor queue, said entries at least indicating locations whereat data buffers are located in the memory; a single channel adapter; a bus operatively coupling the single channel adapter to the memory; a descriptor base address register positioned in the adapter; a descriptor count register positioned in the adapter; a descriptor current address register positioned in the adapter; a descriptor enqueue register positioned in the adapter wherein each of the registers is loaded with control information by said device driver at an initialization period; a memory, in said adapter, that temporarily stores descriptors; and a state machine that accesses selected ones of the registers and transfer descriptors from the descriptor queue to the memory based upon information contained in said selected ones of the registers.

Claim 28

The data transfer mechanism of claim 18 wherein the state machine further causes data to be transferred from the adapter across the bus into the data buffers or from the data buffers across the bus into the adapter.