Multimedia system and method of controlling data transfer between a host system and a network adapter using a DMA engine

Claim 3

The method of claim 1 further including the step of: a) using an arbitration bit in the first descriptor to determine an arbitration level for accesses to the destination.

Claim 4

The method of claim 2 further including the step of: a) using a memory/io bit in the first descriptor to determine if an address represents a micro channel or an io address at the destination in the system.

Claim 5

The method of claim 3 further including the step of: a) using an interrupt after processing bit in the first descriptor to set a DPR bit in a DMA Status Register (DMAS TAT) after processing the first descriptor.

Claim 6

The method of claim 4 further including the step of: a) using a transfer direction bit in the first descriptor to indicate the direction of data transfer between the system and the local bus.

Claim 7

The method of claim 5 further comprising the step of: a) using a no address bit in the first descriptor to determine whether to increment an address in the system.

Claim 8

The method of claim 6 further comprising the step of: a) using a field of least significant bits in the first descriptor to form a low address in a micro channel in the system.

Claim 9

The method of claim 7 further comprising the step of: a) using a field of most significant bits in the first descriptor to form a high address in a micro channel in the system.

Claim 10

The method of claim 8 further comprising the step of: a) using a field of least significant bits in an address portion of the local bus to form a local bus low address.

Claim 11

The method of claim 9 further comprising the step of: a) using a field of most significant bits in an address portion of the local bus to form a local bus high address.

Claim 12

The method of claim 10 further comprising the step of: using a field of 16 least significant bits in an address portion of the local bus to form a link pointer to a next descriptor in a chain of descriptors.

Claim 13

The method of claim 11 further comprising the step of: setting bits in the DMASTAT to indicate error condition or engine aborted or descriptor processed or end of descriptor chain.

Claim 14

The method of claim 12 further comprising the step of: a) forming a DMA engine pointer in the system by using a field of bits in a base address register in the local bus; and b) using a portion of the bits as an engine enable (EEN) bit.

Claim 15

The method of claim 13 further comprising the step of: a) enabling the EEN bit to activate the DMA engine; and b) using the DMA engine to issue the request to a local bus interface of the local bus to fetch the first descriptor.

Claim 16

Apparatus for controlling the delivery of data between a system and an adapter including a local processor, local processor memory and a local bus using a DMA engine, comprising the steps of: a) means for enabling the DMAengine by the local processor; b) means for issuing a request to the local bus interface by the DMA engine to fetch a first descriptor including a byte count field from local memory indicating a source and a destination for the transfer of data between the system and the local bus; c) means for issuing a request to the system and the local bus interface by the DMA engine using the first descriptor for the source to load a FIFO buffer and the destination to unload the FIFO; d) means for issuing a request that the destination empty the FIFO by the DMA when the descriptor byte count becomes zero; e) means for fetching the next descriptor linked to the first descriptor by the DMA engine; and f) means for issuing a request to the system and the local bus interface by the DMA engine for the source to load the FIFO buffer and the destination to unload the FIFO using the next descriptor.

Claim 17

Apparatus for controlling the delivery of data between a system and an adapter including a local processor, local processor memory and a local bus using a DMA engine, comprising the steps of: a) means for enabling the DMAengine by the local processor; b) means for issuing a request to the local bus interface by the DMA engine to fetch a first descriptor including a byte count field from local memory indicating a source and a destination for the transfer of data between the system and the local bus; c) means for issuing a request to the system and the local bus interface by the DMA engine using the first descriptor for the source to load a FIFO buffer and the destination to unload the FIFO; d) means for issuing a request that the destination empty the FIFO by the DMA when the descriptor byte count becomes zero; e) means for fetching the next descriptor linked to the first descriptor by the DMA engine; and f) means for issuing a request to the system and the local bus interface by the DMA engine for the source to load the FIFO buffer and the destination to unload the FIFO using the next descriptor.

Claim 18

The apparatus of claim 15 further comprising: a) a local bus interface for coupling the local bus to the DMA engine and an interface register; and b) a system interface for coupling the system to the DMA engine and the interface register.

Claim 19

The apparatus of claim 16 wherein the DMA engine is a gate array which controls the delivery of data between the system and the local bus.

Claim 20

The apparatus of claim 17 wherein the interface register is a FIFO register.

Claim 21

The apparatus of claim 18 wherein the DMA engine issues bus master requests to the system interface and the local bus interface.

Claim 22

The apparatus of claim 19 wherein the system interface contains a DMA engine pointer that locates a descriptor list in a local bus memory.

Claim 23

The apparatus of claim 20 wherein the system interface contains a status register (DMASTAT) for reporting DMA engine status.

Claim 24

The apparatus of claim 21 further comprising: a) means for terminating the DMA engine activity when an error condition is encountered in transferring data between the local bus and the system; and b) means for disabling an EEN bit in a DMA descriptor pointer.

Claim 25

An article of manufacture comprising: a computer usable medium having computer readable program code means embodied therein for controlling the delivery of data between a system and an adapter including a local processor, local processor memory and a local bus using a DMA engine, the computer readable program code means in said article of manufacture comprising: a) computer readable program code means for enabling the DMA engine by the local processor; b) computer readable program code means for issuing a request to the local bus interface by the DMA engine to fetch a first descriptor including a byte count field from local memory indicating a source and a destination for the transfer of data between the system and the local bus; c) computer readable program code means for issuing a request to the system and the local bus interface by the DMA engine using the first descriptor for the source to load a FIFO buffer and the destination to unload the FIFO; d) computer readable code means for issuing a request that the destination empty the FIFO by the DMA when the descriptor byte count becomes zero; e) computer readable program code means for fetching the next descriptor linked to the first descriptor by the DMA engine; and f) computer readable program code means for issuing a request to the system and the local bus interface by the DMA engine for the source to load the FIFO buffer and the destination to unload the FIFO using the next descriptor.

Claim 26

An article of manufacture comprising: a computer usable medium having computer readable program code means embodied therein for controlling the delivery of data between a system and an adapter including a local processor, local processor memory and a local bus using a DMA engine, the computer readable program code means in said article of manufacture comprising: a) computer readable program code means for enabling the DMA engine by the local processor; b) computer readable program code means for issuing a request to the local bus interface by the DMA engine to fetch a first descriptor including a byte count field from local memory indicating a source and a destination for the transfer of data between the system and the local bus; c) computer readable program code means for issuing a request to the system and the local bus interface by the DMA engine using the first descriptor for the source to load a FIFO buffer and the destination to unload the FIFO; d) computer readable code means for issuing a request that the destination empty the FIFO by the DMA when the descriptor byte count becomes zero; e) computer readable program code means for fetching the next descriptor linked to the first descriptor by the DMA engine; and f) computer readable program code means for issuing a request to the system and the local bus interface by the DMA engine for the source to load the FIFO buffer and the destination to unload the FIFO using the next descriptor.